source: rtems/bsps/sh/gensh1/include/rtems/score/ispsh7032.h @ 2afb22b

5
Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on Dec 23, 2017 at 7:18:56 AM

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

  • Property mode set to 100644
File size: 3.5 KB
Line 
1/*
2 *  This include file contains information pertaining to the Hitachi SH
3 *  processor.
4 *
5 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
6 *           Bernd Becker (becker@faw.uni-ulm.de)
7 *
8 *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
9 *
10 *  This program is distributed in the hope that it will be useful,
11 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
12 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 *
14 *
15 *  COPYRIGHT (c) 1998.
16 *  On-Line Applications Research Corporation (OAR).
17 *
18 *  The license and distribution terms for this file may be
19 *  found in the file LICENSE in this distribution or at
20 *  http://www.rtems.org/license/LICENSE.
21 */
22
23#ifndef __CPU_ISPS_H
24#define __CPU_ISPS_H
25
26#ifdef __cplusplus
27extern "C" {
28#endif
29
30#include <rtems/score/types.h>
31
32extern void __ISR_Handler( uint32_t   vector );
33
34
35/*
36 * interrupt vector table offsets
37 */
38#define NMI_ISP_V 11
39#define USB_ISP_V 12
40#define IRQ0_ISP_V 64
41#define IRQ1_ISP_V 65
42#define IRQ2_ISP_V 66
43#define IRQ3_ISP_V 67
44#define IRQ4_ISP_V 68
45#define IRQ5_ISP_V 69
46#define IRQ6_ISP_V 70
47#define IRQ7_ISP_V 71
48#define DMA0_ISP_V 72
49#define DMA1_ISP_V 74
50#define DMA2_ISP_V 76
51#define DMA3_ISP_V 78
52
53#define IMIA0_ISP_V 80
54#define IMIB0_ISP_V 81
55#define OVI0_ISP_V 82
56
57#define IMIA1_ISP_V 84
58#define IMIB1_ISP_V 85
59#define OVI1_ISP_V 86
60
61#define IMIA2_ISP_V 88
62#define IMIB2_ISP_V 89
63#define OVI2_ISP_V 90
64
65#define IMIA3_ISP_V 92
66#define IMIB3_ISP_V 93
67#define OVI3_ISP_V 94
68
69#define IMIA4_ISP_V 96
70#define IMIB4_ISP_V 97
71#define OVI4_ISP_V 98
72
73#define ERI0_ISP_V 100
74#define RXI0_ISP_V 101
75#define TXI0_ISP_V 102
76#define TEI0_ISP_V 103
77
78#define ERI1_ISP_V 104
79#define RXI1_ISP_V 105
80#define TXI1_ISP_V 106
81#define TEI1_ISP_V 107
82
83#define PRT_ISP_V 108
84#define ADU_ISP_V 109
85#define WDT_ISP_V 112
86#define DREF_ISP_V 113
87
88
89/* dummy ISP */
90extern void _dummy_isp( void );
91
92/* Non Maskable Interrupt */
93extern void _nmi_isp( void );
94
95/* User Break Controller */
96extern void _usb_isp( void );
97
98/* External interrupts 0-7 */
99extern void _irq0_isp( void );
100extern void _irq1_isp( void );
101extern void _irq2_isp( void );
102extern void _irq3_isp( void );
103extern void _irq4_isp( void );
104extern void _irq5_isp( void );
105extern void _irq6_isp( void );
106extern void _irq7_isp( void );
107
108/* DMA - Controller */
109extern void _dma0_isp( void );
110extern void _dma1_isp( void );
111extern void _dma2_isp( void );
112extern void _dma3_isp( void );
113
114/* Interrupt Timer Unit */
115/* Timer 0 */
116extern void _imia0_isp( void );
117extern void _imib0_isp( void );
118extern void _ovi0_isp( void );
119/* Timer 1 */
120extern void _imia1_isp( void );
121extern void _imib1_isp( void );
122extern void _ovi1_isp( void );
123/* Timer 2 */
124extern void _imia2_isp( void );
125extern void _imib2_isp( void );
126extern void _ovi2_isp( void );
127/* Timer 3 */
128extern void _imia3_isp( void );
129extern void _imib3_isp( void );
130extern void _ovi3_isp( void );
131/* Timer 4 */
132extern void _imia4_isp( void );
133extern void _imib4_isp( void );
134extern void _ovi4_isp( void );
135
136/* seriell interfaces */
137extern void _eri0_isp( void );
138extern void _rxi0_isp( void );
139extern void _txi0_isp( void );
140extern void _tei0_isp( void );
141extern void _eri1_isp( void );
142extern void _rxi1_isp( void );
143extern void _txi1_isp( void );
144extern void _tei1_isp( void );
145
146/* Parity Control Unit of the Bus State Controllers */
147extern void _prt_isp( void );
148
149/* ADC */
150extern void _adu_isp( void );
151
152/* Watchdog Timer */
153extern void _wdt_isp( void );
154
155/* DRAM refresh control unit of bus state controller */
156extern void _dref_isp( void );
157
158#ifdef __cplusplus
159}
160#endif
161
162#endif
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