[7908ba5b] | 1 | /* |
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| 2 | * This include file contains information pertaining to the Hitachi SH |
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| 3 | * processor. |
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| 4 | * |
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| 5 | * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and |
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| 6 | * Bernd Becker (becker@faw.uni-ulm.de) |
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| 7 | * |
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| 8 | * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany |
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| 9 | * |
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| 10 | * This program is distributed in the hope that it will be useful, |
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| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
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[3906b3ea] | 13 | * |
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[7908ba5b] | 14 | * |
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| 15 | * COPYRIGHT (c) 1998. |
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| 16 | * On-Line Applications Research Corporation (OAR). |
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| 17 | * |
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| 18 | * The license and distribution terms for this file may be |
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| 19 | * found in the file LICENSE in this distribution or at |
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[c499856] | 20 | * http://www.rtems.org/license/LICENSE. |
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[7908ba5b] | 21 | */ |
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| 22 | |
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| 23 | #ifndef __CPU_ISPS_H |
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| 24 | #define __CPU_ISPS_H |
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| 25 | |
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| 26 | #ifdef __cplusplus |
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| 27 | extern "C" { |
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| 28 | #endif |
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| 29 | |
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[e96a950b] | 30 | extern void __ISR_Handler( uint32_t vector ); |
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[7908ba5b] | 31 | |
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| 32 | |
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| 33 | /* |
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| 34 | * interrupt vector table offsets |
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| 35 | */ |
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| 36 | #define NMI_ISP_V 11 |
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| 37 | #define USB_ISP_V 12 |
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| 38 | #define IRQ0_ISP_V 64 |
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| 39 | #define IRQ1_ISP_V 65 |
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| 40 | #define IRQ2_ISP_V 66 |
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| 41 | #define IRQ3_ISP_V 67 |
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| 42 | #define IRQ4_ISP_V 68 |
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| 43 | #define IRQ5_ISP_V 69 |
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| 44 | #define IRQ6_ISP_V 70 |
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| 45 | #define IRQ7_ISP_V 71 |
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| 46 | #define DMA0_ISP_V 72 |
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| 47 | #define DMA1_ISP_V 74 |
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| 48 | #define DMA2_ISP_V 76 |
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| 49 | #define DMA3_ISP_V 78 |
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| 50 | |
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| 51 | #define IMIA0_ISP_V 80 |
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| 52 | #define IMIB0_ISP_V 81 |
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| 53 | #define OVI0_ISP_V 82 |
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| 54 | |
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| 55 | #define IMIA1_ISP_V 84 |
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| 56 | #define IMIB1_ISP_V 85 |
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| 57 | #define OVI1_ISP_V 86 |
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| 58 | |
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| 59 | #define IMIA2_ISP_V 88 |
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| 60 | #define IMIB2_ISP_V 89 |
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| 61 | #define OVI2_ISP_V 90 |
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| 62 | |
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| 63 | #define IMIA3_ISP_V 92 |
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| 64 | #define IMIB3_ISP_V 93 |
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| 65 | #define OVI3_ISP_V 94 |
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| 66 | |
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| 67 | #define IMIA4_ISP_V 96 |
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| 68 | #define IMIB4_ISP_V 97 |
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| 69 | #define OVI4_ISP_V 98 |
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| 70 | |
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| 71 | #define ERI0_ISP_V 100 |
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| 72 | #define RXI0_ISP_V 101 |
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| 73 | #define TXI0_ISP_V 102 |
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| 74 | #define TEI0_ISP_V 103 |
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| 75 | |
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| 76 | #define ERI1_ISP_V 104 |
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| 77 | #define RXI1_ISP_V 105 |
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| 78 | #define TXI1_ISP_V 106 |
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| 79 | #define TEI1_ISP_V 107 |
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| 80 | |
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| 81 | #define PRT_ISP_V 108 |
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| 82 | #define ADU_ISP_V 109 |
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| 83 | #define WDT_ISP_V 112 |
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| 84 | #define DREF_ISP_V 113 |
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| 85 | |
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| 86 | |
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| 87 | /* dummy ISP */ |
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| 88 | extern void _dummy_isp( void ); |
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| 89 | |
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| 90 | /* Non Maskable Interrupt */ |
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| 91 | extern void _nmi_isp( void ); |
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| 92 | |
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| 93 | /* User Break Controller */ |
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| 94 | extern void _usb_isp( void ); |
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| 95 | |
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| 96 | /* External interrupts 0-7 */ |
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| 97 | extern void _irq0_isp( void ); |
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| 98 | extern void _irq1_isp( void ); |
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| 99 | extern void _irq2_isp( void ); |
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| 100 | extern void _irq3_isp( void ); |
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| 101 | extern void _irq4_isp( void ); |
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| 102 | extern void _irq5_isp( void ); |
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| 103 | extern void _irq6_isp( void ); |
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| 104 | extern void _irq7_isp( void ); |
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| 105 | |
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| 106 | /* DMA - Controller */ |
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| 107 | extern void _dma0_isp( void ); |
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| 108 | extern void _dma1_isp( void ); |
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| 109 | extern void _dma2_isp( void ); |
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| 110 | extern void _dma3_isp( void ); |
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| 111 | |
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| 112 | /* Interrupt Timer Unit */ |
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| 113 | /* Timer 0 */ |
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| 114 | extern void _imia0_isp( void ); |
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| 115 | extern void _imib0_isp( void ); |
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| 116 | extern void _ovi0_isp( void ); |
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| 117 | /* Timer 1 */ |
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| 118 | extern void _imia1_isp( void ); |
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| 119 | extern void _imib1_isp( void ); |
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| 120 | extern void _ovi1_isp( void ); |
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| 121 | /* Timer 2 */ |
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| 122 | extern void _imia2_isp( void ); |
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| 123 | extern void _imib2_isp( void ); |
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| 124 | extern void _ovi2_isp( void ); |
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| 125 | /* Timer 3 */ |
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| 126 | extern void _imia3_isp( void ); |
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| 127 | extern void _imib3_isp( void ); |
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| 128 | extern void _ovi3_isp( void ); |
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| 129 | /* Timer 4 */ |
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| 130 | extern void _imia4_isp( void ); |
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| 131 | extern void _imib4_isp( void ); |
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| 132 | extern void _ovi4_isp( void ); |
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| 133 | |
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| 134 | /* seriell interfaces */ |
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| 135 | extern void _eri0_isp( void ); |
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| 136 | extern void _rxi0_isp( void ); |
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| 137 | extern void _txi0_isp( void ); |
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| 138 | extern void _tei0_isp( void ); |
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| 139 | extern void _eri1_isp( void ); |
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| 140 | extern void _rxi1_isp( void ); |
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| 141 | extern void _txi1_isp( void ); |
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| 142 | extern void _tei1_isp( void ); |
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| 143 | |
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| 144 | /* Parity Control Unit of the Bus State Controllers */ |
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| 145 | extern void _prt_isp( void ); |
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| 146 | |
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| 147 | /* ADC */ |
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| 148 | extern void _adu_isp( void ); |
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| 149 | |
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| 150 | /* Watchdog Timer */ |
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| 151 | extern void _wdt_isp( void ); |
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| 152 | |
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| 153 | /* DRAM refresh control unit of bus state controller */ |
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| 154 | extern void _dref_isp( void ); |
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| 155 | |
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| 156 | #ifdef __cplusplus |
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| 157 | } |
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| 158 | #endif |
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| 159 | |
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| 160 | #endif |
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