| 1 | /* |
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| 2 | * Copyright (c) 2018 embedded brains GmbH |
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| 3 | |
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| 4 | * Copyright (c) 2015 University of York. |
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| 5 | * Hesham Almatary <hesham@alumni.york.ac.uk> |
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| 6 | * |
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| 7 | * Copyright (c) 2013, The Regents of the University of California (Regents). |
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| 8 | * All Rights Reserved. |
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| 9 | * |
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| 10 | * Redistribution and use in source and binary forms, with or without |
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| 11 | * modification, are permitted provided that the following conditions |
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| 12 | * are met: |
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| 13 | * 1. Redistributions of source code must retain the above copyright |
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| 14 | * notice, this list of conditions and the following disclaimer. |
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| 15 | * 2. Redistributions in binary form must reproduce the above copyright |
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| 16 | * notice, this list of conditions and the following disclaimer in the |
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| 17 | * documentation and/or other materials provided with the distribution. |
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| 18 | * |
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| 19 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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| 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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| 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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| 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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| 25 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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| 26 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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| 27 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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| 28 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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| 29 | * SUCH DAMAGE. |
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| 30 | */ |
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| 31 | |
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| 32 | #include <rtems/asm.h> |
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| 33 | #include <rtems/score/percpu.h> |
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| 34 | #include <rtems/score/riscv-utility.h> |
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| 35 | #include <bsp/linker-symbols.h> |
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| 36 | #include <bspopts.h> |
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| 37 | |
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| 38 | PUBLIC(_start) |
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| 39 | |
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| 40 | .section .bsp_start_text, "wax", @progbits |
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| 41 | .align 2 |
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| 42 | |
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| 43 | TYPE_FUNC(_start) |
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| 44 | SYM(_start): |
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| 45 | /* Load global pointer */ |
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| 46 | .option push |
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| 47 | .option norelax |
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| 48 | LADDR gp, __global_pointer$ |
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| 49 | .option pop |
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| 50 | |
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| 51 | /* Init FPU */ |
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| 52 | #ifdef __riscv_flen |
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| 53 | li t0, MSTATUS_FS |
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| 54 | csrs mstatus, t0 |
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| 55 | csrw fcsr, zero |
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| 56 | #endif |
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| 57 | |
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| 58 | /* Set exception handler */ |
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| 59 | LADDR t0, _RISCV_Exception_handler |
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| 60 | csrw mtvec, t0 |
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| 61 | |
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| 62 | /* Load stack pointer and branch to secondary processor start if necessary */ |
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| 63 | #ifdef RTEMS_SMP |
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| 64 | LADDR sp, _ISR_Stack_area_begin |
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| 65 | LADDR t2, _ISR_Stack_size |
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| 66 | csrr s0, mhartid |
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| 67 | LADDR t0, _Per_CPU_Information |
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| 68 | slli t1, s0, PER_CPU_CONTROL_SIZE_LOG2 |
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| 69 | add s1, t0, t1 |
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| 70 | csrw mscratch, s1 |
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| 71 | bnez s0, .Lstart_on_secondary_processor |
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| 72 | add sp, sp, t2 |
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| 73 | #else |
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| 74 | LADDR sp, _ISR_Stack_area_end |
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| 75 | #endif |
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| 76 | |
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| 77 | #ifdef BSP_START_COPY_FDT_FROM_U_BOOT |
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| 78 | mv a0, a1 |
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| 79 | call bsp_fdt_copy |
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| 80 | #endif |
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| 81 | |
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| 82 | /* Clear .bss */ |
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| 83 | LADDR a0, bsp_section_bss_begin |
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| 84 | li a1, 0 |
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| 85 | LADDR a2, bsp_section_bss_size |
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| 86 | call memset |
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| 87 | |
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| 88 | #ifdef RTEMS_SMP |
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| 89 | /* Give go to secondary processors */ |
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| 90 | LADDR t0, .Lsecondary_processor_go |
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| 91 | fence iorw,ow |
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| 92 | amoswap.w zero, zero, 0(t0) |
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| 93 | #endif |
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| 94 | |
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| 95 | li a0, 0 |
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| 96 | j boot_card |
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| 97 | |
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| 98 | #ifdef RTEMS_SMP |
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| 99 | |
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| 100 | .Lstart_on_secondary_processor: |
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| 101 | |
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| 102 | /* Adjust stack pointer */ |
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| 103 | #ifdef __riscv_mul |
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| 104 | addi t0, s0, 1 |
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| 105 | mul t2, t2, t0 |
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| 106 | #else |
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| 107 | mv t0, s0 |
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| 108 | mv t3, t2 |
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| 109 | |
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| 110 | .Ladd_more: |
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| 111 | |
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| 112 | add t2, t2, t3 |
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| 113 | addi t0, t0, -1 |
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| 114 | bnez t0, .Ladd_more |
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| 115 | #endif |
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| 116 | add sp, sp, t2 |
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| 117 | |
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| 118 | /* Wait for go issued by the boot processor (mhartid == 0) */ |
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| 119 | LADDR t0, .Lsecondary_processor_go |
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| 120 | |
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| 121 | .Lwait_for_go_again: |
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| 122 | |
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| 123 | lw t1, 0(t0) |
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| 124 | fence iorw, iorw |
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| 125 | bnez t1, .Lwait_for_go_again |
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| 126 | |
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| 127 | mv a0, s1 |
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| 128 | call bsp_start_on_secondary_processor |
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| 129 | |
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| 130 | #if __riscv_xlen == 32 |
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| 131 | .align 2 |
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| 132 | #elif __riscv_xlen == 64 |
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| 133 | .align 3 |
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| 134 | #endif |
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| 135 | |
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| 136 | .Lsecondary_processor_go: |
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| 137 | |
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| 138 | /* |
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| 139 | * These are ebreak instructions, just in case we end up here executing |
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| 140 | * code. |
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| 141 | */ |
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| 142 | .word 0x00100073 |
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| 143 | #if __riscv_xlen == 64 |
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| 144 | .word 0x00100073 |
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| 145 | #endif |
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| 146 | |
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| 147 | #endif /* RTEMS_SMP */ |
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![[RTEMS Logo]](/images/logo.png){kind=logo}
