source: rtems/bsps/riscv/riscv/start/start.S @ ff081aee

Last change on this file since ff081aee was ff081aee, checked in by Sebastian Huber <sebastian.huber@…>, on Nov 6, 2018 at 3:58:02 PM

score: Rename interrupt stack symbols

Rename

  • _Configuration_Interrupt_stack_area_begin in _ISR_Stack_area_begin,
  • _Configuration_Interrupt_stack_area_end in _ISR_Stack_area_end, and
  • _Configuration_Interrupt_stack_size in _ISR_Stack_size.

Move definitions to <rtems/score/isr.h>. The new names are considerable
shorter and in the right namespace.

Update #3459.

  • Property mode set to 100644
File size: 3.5 KB
Line 
1/*
2 * Copyright (c) 2018 embedded brains GmbH
3
4 * Copyright (c) 2015 University of York.
5 * Hesham Almatary <hesham@alumni.york.ac.uk>
6 *
7 * Copyright (c) 2013, The Regents of the University of California (Regents).
8 * All Rights Reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32#include <rtems/asm.h>
33#include <rtems/score/percpu.h>
34#include <rtems/score/riscv-utility.h>
35#include <bsp/linker-symbols.h>
36#include <bspopts.h>
37
38PUBLIC(_start)
39
40        .section        .bsp_start_text, "wax", @progbits
41        .align  2
42
43TYPE_FUNC(_start)
44SYM(_start):
45        /* Load global pointer */
46        .option push
47        .option norelax
48        LADDR   gp, __global_pointer$
49        .option pop
50
51        /* Init FPU */
52#ifdef __riscv_flen
53        li      t0, MSTATUS_FS
54        csrs    mstatus, t0
55        csrw    fcsr, zero
56#endif
57
58        /* Set exception handler */
59        LADDR   t0, _RISCV_Exception_handler
60        csrw    mtvec, t0
61
62        /* Load stack pointer and branch to secondary processor start if necessary */
63#ifdef RTEMS_SMP
64        LADDR   sp, _ISR_Stack_area_begin
65        LADDR   t2, _ISR_Stack_size
66        csrr    s0, mhartid
67        LADDR   t0, _Per_CPU_Information
68        slli    t1, s0, PER_CPU_CONTROL_SIZE_LOG2
69        add     s1, t0, t1
70        csrw    mscratch, s1
71        bnez    s0, .Lstart_on_secondary_processor
72        add     sp, sp, t2
73#else
74        LADDR   sp, _ISR_Stack_area_end
75#endif
76
77#ifdef BSP_START_COPY_FDT_FROM_U_BOOT
78        mv      a0, a1
79        call    bsp_fdt_copy
80#endif
81
82        /* Clear .bss */
83        LADDR   a0, bsp_section_bss_begin
84        li      a1, 0
85        LADDR   a2, bsp_section_bss_size
86        call    memset
87
88#ifdef RTEMS_SMP
89        /* Give go to secondary processors */
90        LADDR   t0, .Lsecondary_processor_go
91        fence   iorw,ow
92        amoswap.w       zero, zero, 0(t0)
93#endif
94
95        j       boot_card
96
97#ifdef RTEMS_SMP
98
99.Lstart_on_secondary_processor:
100
101        /* Adjust stack pointer */
102#ifdef __riscv_mul
103        addi    t0, s0, 1
104        mul     t2, t2, t0
105#else
106        mv      t0, s0
107        mv      t3, t2
108
109.Ladd_more:
110
111        add     t2, t2, t3
112        addi    t0, t0, -1
113        bnez    t0, .Ladd_more
114#endif
115        add     sp, sp, t2
116
117        /* Wait for go issued by the boot processor (mhartid == 0) */
118        LADDR   t0, .Lsecondary_processor_go
119
120.Lwait_for_go_again:
121
122        lw      t1, 0(t0)
123        fence   iorw, iorw
124        bnez    t1, .Lwait_for_go_again
125
126        mv      a0, s1
127        call    bsp_start_on_secondary_processor
128
129#if __riscv_xlen == 32
130        .align  2
131#elif __riscv_xlen == 64
132        .align  3
133#endif
134
135.Lsecondary_processor_go:
136
137        /*
138         * These are ebreak instructions, just in case we end up here executing
139         * code.
140         */
141        .word   0x00100073
142#if __riscv_xlen == 64
143        .word   0x00100073
144#endif
145
146#endif /* RTEMS_SMP */
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