source: rtems/bsps/riscv/riscv/start/start.S @ fe2cd01

Last change on this file since fe2cd01 was fe2cd01, checked in by Sebastian Huber <sebastian.huber@…>, on Jun 22, 2018 at 6:01:48 AM

bsp/riscv: Add device tree support

Update #3433.

  • Property mode set to 100644
File size: 3.3 KB
Line 
1/*
2 * Copyright (c) 2015 University of York.
3 * Hesham Almatary <hesham@alumni.york.ac.uk>
4 *
5 * Copyright (c) 2013, The Regents of the University of California (Regents).
6 * All Rights Reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30#include <rtems/asm.h>
31#include <rtems/score/cpu.h>
32#include <rtems/score/riscv-utility.h>
33#include <bsp/linker-symbols.h>
34#include <bspopts.h>
35
36EXTERN(bsp_section_bss_begin)
37EXTERN(bsp_section_bss_end)
38EXTERN(ISR_Handler)
39EXTERN(bsp_section_stack_begin)
40
41PUBLIC(bsp_start_vector_table_begin)
42PUBLIC(bsp_start_vector_table_end)
43PUBLIC(_start)
44
45        .section        .bsp_start_text, "ax", @progbits
46        .align  2
47
48TYPE_FUNC(_start)
49SYM(_start):
50        /* Load global pointer */
51        .option push
52        .option norelax
53        la      gp, __global_pointer$
54        .option pop
55
56#ifdef RTEMS_SMP
57        csrr    s0, mhartid
58        bnez    s0, .Lloop_forever
59#endif
60
61        /* load stack and frame pointers */
62        la      sp, _Configuration_Interrupt_stack_area_end
63
64#ifdef BSP_START_COPY_FDT_FROM_U_BOOT
65        mv      a0, a1
66        call    bsp_fdt_copy
67#endif
68
69        la      t0, ISR_Handler
70        csrw    mtvec, t0
71
72        /* Clear .bss */
73        la      a0, bsp_section_bss_begin
74        li      a1, 0
75        la      a2, bsp_section_bss_size
76        call    memset
77
78        /* Init FPU unit if it's there */
79        li      t0, MSTATUS_FS
80        csrs    mstatus, t0
81
82        j       boot_card
83
84#ifdef RTEMS_SMP
85.Lloop_forever:
86        j       .Lloop_forever
87#endif
88
89        .align  4
90bsp_start_vector_table_begin:
91        .word   _RISCV_Exception_default /* User int */
92        .word   _RISCV_Exception_default /* Supervisor int */
93        .word   _RISCV_Exception_default /* Reserved */
94        .word   _RISCV_Exception_default /* Machine int */
95        .word   _RISCV_Exception_default /* User timer int */
96        .word   _RISCV_Exception_default /* Supervisor Timer int */
97        .word   _RISCV_Exception_default /* Reserved */
98        .word   _RISCV_Exception_default /* Machine Timer int */
99        .word   _RISCV_Exception_default /* User external int */
100        .word   _RISCV_Exception_default /* Supervisor external int */
101        .word   _RISCV_Exception_default /* Reserved */
102        .word   _RISCV_Exception_default /* Machine external int */
103        .word   _RISCV_Exception_default
104        .word   _RISCV_Exception_default
105        .word   _RISCV_Exception_default
106        .word   _RISCV_Exception_default
107bsp_start_vector_table_end:
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