source: rtems/bsps/riscv/riscv/start/start.S @ c558cc4

Last change on this file since c558cc4 was c558cc4, checked in by Sebastian Huber <sebastian.huber@…>, on Jun 28, 2018 at 11:04:58 AM

bsp/riscv: Fix vector table for lp64

Update #3433.

  • Property mode set to 100644
File size: 3.7 KB
Line 
1/*
2 * Copyright (c) 2015 University of York.
3 * Hesham Almatary <hesham@alumni.york.ac.uk>
4 *
5 * Copyright (c) 2013, The Regents of the University of California (Regents).
6 * All Rights Reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30#include <rtems/asm.h>
31#include <rtems/score/cpu.h>
32#include <rtems/score/riscv-utility.h>
33#include <bsp/linker-symbols.h>
34#include <bspopts.h>
35
36EXTERN(bsp_section_bss_begin)
37EXTERN(bsp_section_bss_end)
38EXTERN(ISR_Handler)
39EXTERN(bsp_section_stack_begin)
40
41PUBLIC(bsp_start_vector_table_begin)
42PUBLIC(bsp_start_vector_table_end)
43PUBLIC(_start)
44
45        .section        .bsp_start_text, "wax", @progbits
46        .align  2
47
48TYPE_FUNC(_start)
49SYM(_start):
50        /* Load global pointer */
51        .option push
52        .option norelax
53        la      gp, __global_pointer$
54        .option pop
55
56#ifdef RTEMS_SMP
57        csrr    s0, mhartid
58        bnez    s0, .Lwait_for_go
59#endif
60
61        /* load stack and frame pointers */
62        la      sp, _Configuration_Interrupt_stack_area_end
63
64#ifdef BSP_START_COPY_FDT_FROM_U_BOOT
65        mv      a0, a1
66        call    bsp_fdt_copy
67#endif
68
69        la      t0, ISR_Handler
70        csrw    mtvec, t0
71
72        /* Clear .bss */
73        la      a0, bsp_section_bss_begin
74        li      a1, 0
75        la      a2, bsp_section_bss_size
76        call    memset
77
78#ifdef RTEMS_SMP
79        /* Give go to secondary processors */
80        la      t0, .Lsecondary_processor_go
81        fence   iorw,ow
82        amoswap.w       zero, zero, 0(t0)
83#endif
84
85        /* Init FPU unit if it's there */
86        li      t0, MSTATUS_FS
87        csrs    mstatus, t0
88
89        j       boot_card
90
91#ifdef RTEMS_SMP
92        /* Wait for go issued by the boot processor (mhartid == 0) */
93.Lwait_for_go:
94        la      t0, .Lsecondary_processor_go
95.Lwait_for_go_again:
96        lw      t1, 0(t0)
97        fence   iorw, iorw
98        sext.w  t1, t1
99        bnez    t1, .Lwait_for_go_again
100.Lloop_forever:
101        j       .Lloop_forever
102
103.Lsecondary_processor_go:
104        .word   0xdeadbeef
105#endif
106
107#if __riscv_xlen == 32
108#define ADDR .word
109#elif __riscv_xlen == 64
110#define ADDR .quad
111#endif
112
113        .align  4
114bsp_start_vector_table_begin:
115        ADDR    _RISCV_Exception_default /* User int */
116        ADDR    _RISCV_Exception_default /* Supervisor int */
117        ADDR    _RISCV_Exception_default /* Reserved */
118        ADDR    _RISCV_Exception_default /* Machine int */
119        ADDR    _RISCV_Exception_default /* User timer int */
120        ADDR    _RISCV_Exception_default /* Supervisor Timer int */
121        ADDR    _RISCV_Exception_default /* Reserved */
122        ADDR    _RISCV_Exception_default /* Machine Timer int */
123        ADDR    _RISCV_Exception_default /* User external int */
124        ADDR    _RISCV_Exception_default /* Supervisor external int */
125        ADDR    _RISCV_Exception_default /* Reserved */
126        ADDR    _RISCV_Exception_default /* Machine external int */
127        ADDR    _RISCV_Exception_default
128        ADDR    _RISCV_Exception_default
129        ADDR    _RISCV_Exception_default
130        ADDR    _RISCV_Exception_default
131bsp_start_vector_table_end:
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