source: rtems/bsps/riscv/riscv/start/start.S @ bca36d9

Last change on this file since bca36d9 was bca36d9, checked in by Sebastian Huber <sebastian.huber@…>, on Jul 6, 2018 at 9:07:20 AM

riscv: Add LADDR assembler define

An address must be loaded to a register according to the code model.
Add LADDR define for use in assembler code.

Update #3433.

  • Property mode set to 100644
File size: 3.9 KB
Line 
1/*
2 * Copyright (c) 2015 University of York.
3 * Hesham Almatary <hesham@alumni.york.ac.uk>
4 *
5 * Copyright (c) 2013, The Regents of the University of California (Regents).
6 * All Rights Reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30#include <rtems/asm.h>
31#include <rtems/score/percpu.h>
32#include <rtems/score/riscv-utility.h>
33#include <bsp/linker-symbols.h>
34#include <bspopts.h>
35
36EXTERN(bsp_section_bss_begin)
37EXTERN(bsp_section_bss_end)
38EXTERN(ISR_Handler)
39EXTERN(bsp_section_stack_begin)
40
41PUBLIC(bsp_start_vector_table_begin)
42PUBLIC(bsp_start_vector_table_end)
43PUBLIC(_start)
44
45        .section        .bsp_start_text, "wax", @progbits
46        .align  2
47
48TYPE_FUNC(_start)
49SYM(_start):
50        /* Load global pointer */
51        .option push
52        .option norelax
53        LADDR   gp, __global_pointer$
54        .option pop
55
56#ifdef RTEMS_SMP
57        csrr    s0, mhartid
58        LADDR   t0, _Per_CPU_Information
59        slli    t1, s0, PER_CPU_CONTROL_SIZE_LOG2
60        add     t0, t0, t1
61        csrw    mscratch, t0
62        bnez    s0, .Lwait_for_go
63#endif
64
65        /* load stack and frame pointers */
66        LADDR   sp, _Configuration_Interrupt_stack_area_end
67
68#ifdef BSP_START_COPY_FDT_FROM_U_BOOT
69        mv      a0, a1
70        call    bsp_fdt_copy
71#endif
72
73        LADDR   t0, ISR_Handler
74        csrw    mtvec, t0
75
76        /* Clear .bss */
77        LADDR   a0, bsp_section_bss_begin
78        li      a1, 0
79        LADDR   a2, bsp_section_bss_size
80        call    memset
81
82#ifdef RTEMS_SMP
83        /* Give go to secondary processors */
84        LADDR   t0, .Lsecondary_processor_go
85        fence   iorw,ow
86        amoswap.w       zero, zero, 0(t0)
87#endif
88
89        /* Init FPU unit if it's there */
90        li      t0, MSTATUS_FS
91        csrs    mstatus, t0
92
93        j       boot_card
94
95#ifdef RTEMS_SMP
96        /* Wait for go issued by the boot processor (mhartid == 0) */
97.Lwait_for_go:
98        LADDR   t0, .Lsecondary_processor_go
99.Lwait_for_go_again:
100        lw      t1, 0(t0)
101        fence   iorw, iorw
102        sext.w  t1, t1
103        bnez    t1, .Lwait_for_go_again
104.Lloop_forever:
105        j       .Lloop_forever
106
107.Lsecondary_processor_go:
108        .word   0xdeadbeef
109#endif
110
111#if __riscv_xlen == 32
112#define ADDR .word
113#elif __riscv_xlen == 64
114#define ADDR .quad
115#endif
116
117        .align  4
118bsp_start_vector_table_begin:
119        ADDR    _RISCV_Exception_default /* User int */
120        ADDR    _RISCV_Exception_default /* Supervisor int */
121        ADDR    _RISCV_Exception_default /* Reserved */
122        ADDR    _RISCV_Exception_default /* Machine int */
123        ADDR    _RISCV_Exception_default /* User timer int */
124        ADDR    _RISCV_Exception_default /* Supervisor Timer int */
125        ADDR    _RISCV_Exception_default /* Reserved */
126        ADDR    _RISCV_Exception_default /* Machine Timer int */
127        ADDR    _RISCV_Exception_default /* User external int */
128        ADDR    _RISCV_Exception_default /* Supervisor external int */
129        ADDR    _RISCV_Exception_default /* Reserved */
130        ADDR    _RISCV_Exception_default /* Machine external int */
131        ADDR    _RISCV_Exception_default
132        ADDR    _RISCV_Exception_default
133        ADDR    _RISCV_Exception_default
134        ADDR    _RISCV_Exception_default
135bsp_start_vector_table_end:
Note: See TracBrowser for help on using the repository browser.