source: rtems/bsps/riscv/riscv/start/start.S @ 9b2ef07f

Last change on this file since 9b2ef07f was 9b2ef07f, checked in by Sebastian Huber <sebastian.huber@…>, on Jun 22, 2018 at 11:30:21 AM

bsp/riscv: Load global pointer

Update #3433.

  • Property mode set to 100644
File size: 3.1 KB
Line 
1/*
2 * Copyright (c) 2015 University of York.
3 * Hesham Almatary <hesham@alumni.york.ac.uk>
4 *
5 * Copyright (c) 2013, The Regents of the University of California (Regents).
6 * All Rights Reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30#include <bsp/linker-symbols.h>
31#include <rtems/score/riscv-utility.h>
32#include <rtems/score/cpu.h>
33#include <rtems/asm.h>
34
35EXTERN(bsp_section_bss_begin)
36EXTERN(bsp_section_bss_end)
37EXTERN(ISR_Handler)
38EXTERN(bsp_section_stack_begin)
39
40PUBLIC(bsp_start_vector_table_begin)
41PUBLIC(bsp_start_vector_table_end)
42PUBLIC(_start)
43
44        .section        .bsp_start_text, "ax", @progbits
45        .align  2
46
47TYPE_FUNC(_start)
48SYM(_start):
49        /* Load global pointer */
50        .option push
51        .option norelax
52        la      gp, __global_pointer$
53        .option pop
54
55        la      t0, ISR_Handler
56        csrw    mtvec, t0
57
58        /* load stack and frame pointers */
59        la      sp, _Configuration_Interrupt_stack_area_end
60
61        /* Clear .bss */
62        la      a0, bsp_section_bss_begin
63        li      a1, 0
64        la      a2, bsp_section_bss_size
65        call    memset
66
67        /* Init FPU unit if it's there */
68        li      t0, MSTATUS_FS
69        csrs    mstatus, t0
70
71        j       boot_card
72
73        .align  4
74bsp_start_vector_table_begin:
75        .word   _RISCV_Exception_default /* User int */
76        .word   _RISCV_Exception_default /* Supervisor int */
77        .word   _RISCV_Exception_default /* Reserved */
78        .word   _RISCV_Exception_default /* Machine int */
79        .word   _RISCV_Exception_default /* User timer int */
80        .word   _RISCV_Exception_default /* Supervisor Timer int */
81        .word   _RISCV_Exception_default /* Reserved */
82        .word   _RISCV_Exception_default /* Machine Timer int */
83        .word   _RISCV_Exception_default /* User external int */
84        .word   _RISCV_Exception_default /* Supervisor external int */
85        .word   _RISCV_Exception_default /* Reserved */
86        .word   _RISCV_Exception_default /* Machine external int */
87        .word   _RISCV_Exception_default
88        .word   _RISCV_Exception_default
89        .word   _RISCV_Exception_default
90        .word   _RISCV_Exception_default
91bsp_start_vector_table_end:
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