| 1 | /* |
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| 2 | * Copyright (c) 2015 University of York. |
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| 3 | * Hesham Almatary <hesham@alumni.york.ac.uk> |
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| 4 | * |
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| 5 | * Copyright (c) 2013, The Regents of the University of California (Regents). |
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| 6 | * All Rights Reserved. |
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| 7 | * |
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| 8 | * Redistribution and use in source and binary forms, with or without |
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| 9 | * modification, are permitted provided that the following conditions |
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| 10 | * are met: |
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| 11 | * 1. Redistributions of source code must retain the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer. |
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| 13 | * 2. Redistributions in binary form must reproduce the above copyright |
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| 14 | * notice, this list of conditions and the following disclaimer in the |
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| 15 | * documentation and/or other materials provided with the distribution. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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| 18 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 19 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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| 21 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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| 22 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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| 23 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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| 24 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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| 25 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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| 26 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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| 27 | * SUCH DAMAGE. |
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| 28 | */ |
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| 29 | #include <bsp/linker-symbols.h> |
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| 30 | #include <rtems/score/riscv-utility.h> |
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| 31 | #include <rtems/score/cpu.h> |
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| 32 | #include <rtems/asm.h> |
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| 33 | |
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| 34 | EXTERN(bsp_section_bss_begin) |
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| 35 | EXTERN(bsp_section_bss_end) |
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| 36 | EXTERN(ISR_Handler) |
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| 37 | EXTERN(bsp_section_stack_begin) |
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| 38 | |
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| 39 | PUBLIC(bsp_start_vector_table_begin) |
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| 40 | PUBLIC(bsp_start_vector_table_end) |
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| 41 | PUBLIC(_start) |
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| 42 | |
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| 43 | .section .bsp_start_text, "wax" |
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| 44 | TYPE_FUNC(_start) |
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| 45 | SYM(_start): |
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| 46 | li x2, 0 |
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| 47 | li x3, 0 |
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| 48 | li x4, 0 |
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| 49 | li x5, 0 |
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| 50 | li x6, 0 |
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| 51 | li x7, 0 |
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| 52 | li x8, 0 |
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| 53 | li x9, 0 |
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| 54 | li x10, 0 |
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| 55 | li x11, 0 |
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| 56 | li x12, 0 |
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| 57 | li x13, 0 |
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| 58 | li x14, 0 |
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| 59 | li x15, 0 |
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| 60 | li x16, 0 |
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| 61 | li x17, 0 |
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| 62 | li x18, 0 |
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| 63 | li x19, 0 |
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| 64 | li x20, 0 |
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| 65 | li x21, 0 |
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| 66 | li x22, 0 |
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| 67 | li x23, 0 |
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| 68 | li x24, 0 |
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| 69 | li x25, 0 |
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| 70 | li x26, 0 |
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| 71 | li x27, 0 |
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| 72 | li x28, 0 |
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| 73 | li x29, 0 |
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| 74 | li x30, 0 |
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| 75 | li x31, 0 |
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| 76 | |
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| 77 | la t0, ISR_Handler |
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| 78 | csrw mtvec, t0 |
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| 79 | |
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| 80 | /* load stack and frame pointers */ |
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| 81 | la sp, _Configuration_Interrupt_stack_area_end |
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| 82 | |
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| 83 | /* Clearing .bss */ |
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| 84 | la t0, bsp_section_bss_begin |
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| 85 | la t1, bsp_section_bss_end |
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| 86 | |
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| 87 | _loop_clear_bss: |
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| 88 | bge t0, t1, _end_clear_bss |
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| 89 | SREG x0, 0(t0) |
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| 90 | addi t0, t0, CPU_SIZEOF_POINTER |
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| 91 | j _loop_clear_bss |
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| 92 | _end_clear_bss: |
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| 93 | |
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| 94 | /* Init FPU unit if it's there */ |
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| 95 | li t0, MSTATUS_FS |
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| 96 | csrs mstatus, t0 |
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| 97 | |
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| 98 | j boot_card |
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| 99 | |
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| 100 | .align 4 |
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| 101 | bsp_start_vector_table_begin: |
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| 102 | .word _RISCV_Exception_default /* User int */ |
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| 103 | .word _RISCV_Exception_default /* Supervisor int */ |
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| 104 | .word _RISCV_Exception_default /* Reserved */ |
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| 105 | .word _RISCV_Exception_default /* Machine int */ |
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| 106 | .word _RISCV_Exception_default /* User timer int */ |
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| 107 | .word _RISCV_Exception_default /* Supervisor Timer int */ |
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| 108 | .word _RISCV_Exception_default /* Reserved */ |
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| 109 | .word _RISCV_Exception_default /* Machine Timer int */ |
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| 110 | .word _RISCV_Exception_default /* User external int */ |
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| 111 | .word _RISCV_Exception_default /* Supervisor external int */ |
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| 112 | .word _RISCV_Exception_default /* Reserved */ |
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| 113 | .word _RISCV_Exception_default /* Machine external int */ |
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| 114 | .word _RISCV_Exception_default |
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| 115 | .word _RISCV_Exception_default |
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| 116 | .word _RISCV_Exception_default |
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| 117 | .word _RISCV_Exception_default |
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| 118 | bsp_start_vector_table_end: |
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