| 1 | /* |
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| 2 | * Copyright (c) 2015 University of York. |
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| 3 | * Hesham Almatary <hesham@alumni.york.ac.uk> |
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| 4 | * |
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| 5 | * Copyright (c) 2013, The Regents of the University of California (Regents). |
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| 6 | * All Rights Reserved. |
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| 7 | * |
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| 8 | * Redistribution and use in source and binary forms, with or without |
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| 9 | * modification, are permitted provided that the following conditions |
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| 10 | * are met: |
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| 11 | * 1. Redistributions of source code must retain the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer. |
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| 13 | * 2. Redistributions in binary form must reproduce the above copyright |
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| 14 | * notice, this list of conditions and the following disclaimer in the |
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| 15 | * documentation and/or other materials provided with the distribution. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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| 18 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 19 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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| 21 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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| 22 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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| 23 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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| 24 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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| 25 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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| 26 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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| 27 | * SUCH DAMAGE. |
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| 28 | */ |
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| 29 | |
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| 30 | #include <rtems/asm.h> |
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| 31 | #include <rtems/score/cpu.h> |
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| 32 | #include <rtems/score/riscv-utility.h> |
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| 33 | #include <bsp/linker-symbols.h> |
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| 34 | #include <bspopts.h> |
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| 35 | |
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| 36 | EXTERN(bsp_section_bss_begin) |
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| 37 | EXTERN(bsp_section_bss_end) |
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| 38 | EXTERN(ISR_Handler) |
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| 39 | EXTERN(bsp_section_stack_begin) |
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| 40 | |
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| 41 | PUBLIC(bsp_start_vector_table_begin) |
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| 42 | PUBLIC(bsp_start_vector_table_end) |
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| 43 | PUBLIC(_start) |
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| 44 | |
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| 45 | .section .bsp_start_text, "wax", @progbits |
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| 46 | .align 2 |
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| 47 | |
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| 48 | TYPE_FUNC(_start) |
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| 49 | SYM(_start): |
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| 50 | /* Load global pointer */ |
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| 51 | .option push |
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| 52 | .option norelax |
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| 53 | la gp, __global_pointer$ |
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| 54 | .option pop |
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| 55 | |
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| 56 | #ifdef RTEMS_SMP |
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| 57 | csrr s0, mhartid |
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| 58 | bnez s0, .Lwait_for_go |
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| 59 | #endif |
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| 60 | |
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| 61 | /* load stack and frame pointers */ |
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| 62 | la sp, _Configuration_Interrupt_stack_area_end |
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| 63 | |
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| 64 | #ifdef BSP_START_COPY_FDT_FROM_U_BOOT |
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| 65 | mv a0, a1 |
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| 66 | call bsp_fdt_copy |
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| 67 | #endif |
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| 68 | |
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| 69 | la t0, ISR_Handler |
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| 70 | csrw mtvec, t0 |
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| 71 | |
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| 72 | /* Clear .bss */ |
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| 73 | la a0, bsp_section_bss_begin |
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| 74 | li a1, 0 |
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| 75 | la a2, bsp_section_bss_size |
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| 76 | call memset |
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| 77 | |
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| 78 | #ifdef RTEMS_SMP |
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| 79 | /* Give go to secondary processors */ |
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| 80 | la t0, .Lsecondary_processor_go |
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| 81 | fence iorw,ow |
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| 82 | amoswap.w zero, zero, 0(t0) |
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| 83 | #endif |
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| 84 | |
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| 85 | /* Init FPU unit if it's there */ |
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| 86 | li t0, MSTATUS_FS |
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| 87 | csrs mstatus, t0 |
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| 88 | |
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| 89 | j boot_card |
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| 90 | |
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| 91 | #ifdef RTEMS_SMP |
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| 92 | /* Wait for go issued by the boot processor (mhartid == 0) */ |
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| 93 | .Lwait_for_go: |
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| 94 | la t0, .Lsecondary_processor_go |
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| 95 | .Lwait_for_go_again: |
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| 96 | lw t1, 0(t0) |
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| 97 | fence iorw, iorw |
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| 98 | sext.w t1, t1 |
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| 99 | bnez t1, .Lwait_for_go_again |
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| 100 | .Lloop_forever: |
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| 101 | j .Lloop_forever |
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| 102 | |
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| 103 | .Lsecondary_processor_go: |
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| 104 | .word 0xdeadbeef |
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| 105 | #endif |
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| 106 | |
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| 107 | #if __riscv_xlen == 32 |
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| 108 | #define ADDR .word |
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| 109 | #elif __riscv_xlen == 64 |
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| 110 | #define ADDR .quad |
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| 111 | #endif |
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| 112 | |
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| 113 | .align 4 |
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| 114 | bsp_start_vector_table_begin: |
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| 115 | ADDR _RISCV_Exception_default /* User int */ |
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| 116 | ADDR _RISCV_Exception_default /* Supervisor int */ |
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| 117 | ADDR _RISCV_Exception_default /* Reserved */ |
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| 118 | ADDR _RISCV_Exception_default /* Machine int */ |
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| 119 | ADDR _RISCV_Exception_default /* User timer int */ |
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| 120 | ADDR _RISCV_Exception_default /* Supervisor Timer int */ |
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| 121 | ADDR _RISCV_Exception_default /* Reserved */ |
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| 122 | ADDR _RISCV_Exception_default /* Machine Timer int */ |
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| 123 | ADDR _RISCV_Exception_default /* User external int */ |
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| 124 | ADDR _RISCV_Exception_default /* Supervisor external int */ |
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| 125 | ADDR _RISCV_Exception_default /* Reserved */ |
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| 126 | ADDR _RISCV_Exception_default /* Machine external int */ |
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| 127 | ADDR _RISCV_Exception_default |
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| 128 | ADDR _RISCV_Exception_default |
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| 129 | ADDR _RISCV_Exception_default |
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| 130 | ADDR _RISCV_Exception_default |
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| 131 | bsp_start_vector_table_end: |
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