source: rtems/bsps/riscv/riscv/start/bspsmp.c @ 447fd89

5
Last change on this file since 447fd89 was 447fd89, checked in by Sebastian Huber <sebastian.huber@…>, on 07/20/18 at 11:11:04

bsp/riscv: Add basic SMP startup

Update #3433.

  • Property mode set to 100644
File size: 2.3 KB
Line 
1/*
2 * Copyright (c) 2018 embedded brains GmbH
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 *    notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 *    notice, this list of conditions and the following disclaimer in the
11 *    documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26#include <bsp/bootcard.h>
27#include <bsp/irq.h>
28#include <bsp/riscv.h>
29
30#include <rtems/score/riscv-utility.h>
31#include <rtems/score/smpimpl.h>
32
33void bsp_start_on_secondary_processor(Per_CPU_Control *cpu_self)
34{
35  uint32_t cpu_index_self;
36
37  cpu_index_self = _Per_CPU_Get_index(cpu_self);
38
39  if (
40    cpu_index_self < rtems_configuration_get_maximum_processors()
41      && _SMP_Should_start_processor(cpu_index_self)
42  ) {
43    set_csr(mie, MIP_MSIP);
44    _SMP_Start_multitasking_on_secondary_processor(cpu_self);
45  } else {
46    _CPU_Thread_Idle_body(0);
47  }
48}
49
50uint32_t _CPU_SMP_Initialize(void)
51{
52  return riscv_hart_count;
53}
54
55bool _CPU_SMP_Start_processor(uint32_t cpu_index)
56{
57  return true;
58}
59
60void _CPU_SMP_Finalize_initialization(uint32_t cpu_count)
61{
62  (void) cpu_count;
63  set_csr(mie, MIP_MSIP);
64}
65
66void _CPU_SMP_Prepare_start_multitasking(void)
67{
68  /* Do nothing */
69}
70
71void _CPU_SMP_Send_interrupt(uint32_t target_processor_index)
72{
73  Per_CPU_Control *cpu;
74
75  cpu = _Per_CPU_Get_by_index(target_processor_index);
76  *cpu->cpu_per_cpu.clint_msip = 0x1;
77}
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