1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup riscv_interrupt |
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5 | * |
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6 | * @brief Interrupt support. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2018 embedded brains GmbH |
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11 | * |
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12 | * Copyright (c) 2015 University of York. |
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13 | * Hesham Almatary <hesham@alumni.york.ac.uk> |
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14 | * |
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15 | * Redistribution and use in source and binary forms, with or without |
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16 | * modification, are permitted provided that the following conditions |
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17 | * are met: |
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18 | * 1. Redistributions of source code must retain the above copyright |
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19 | * notice, this list of conditions and the following disclaimer. |
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20 | * 2. Redistributions in binary form must reproduce the above copyright |
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21 | * notice, this list of conditions and the following disclaimer in the |
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22 | * documentation and/or other materials provided with the distribution. |
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23 | * |
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24 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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25 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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27 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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30 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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31 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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32 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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33 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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34 | * SUCH DAMAGE. |
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35 | */ |
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36 | |
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37 | #include <bsp/irq.h> |
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38 | #include <bsp/fatal.h> |
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39 | #include <bsp/fdt.h> |
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40 | #include <bsp/irq-generic.h> |
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41 | #include <bsp/riscv.h> |
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42 | |
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43 | #include <rtems/score/percpu.h> |
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44 | #include <rtems/score/riscv-utility.h> |
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45 | #include <rtems/score/smpimpl.h> |
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46 | |
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47 | #include <libfdt.h> |
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48 | |
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49 | volatile RISCV_CLINT_regs *riscv_clint; |
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50 | |
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51 | /* |
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52 | * The lovely PLIC has an interrupt enable bit per hart for each interrupt |
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53 | * source. This makes the interrupt enable/disable a bit difficult. We have |
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54 | * to store the interrupt distribution in software. To keep it simple, we |
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55 | * support only a one-to-one and one-to-all interrupt to processor |
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56 | * distribution. For a one-to-one distribution, the array member must point to |
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57 | * the enable register block of the corresponding. For a one-to-all |
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58 | * distribution, the array member must be NULL. The array index is the |
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59 | * external interrupt index minus one (external interrupt index zero is a |
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60 | * special value, see PLIC documentation). |
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61 | */ |
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62 | static volatile uint32_t * |
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63 | riscv_plic_irq_to_cpu[RISCV_MAXIMUM_EXTERNAL_INTERRUPTS]; |
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64 | |
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65 | RTEMS_INTERRUPT_LOCK_DEFINE(static, riscv_plic_lock, "PLIC") |
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66 | |
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67 | void _RISCV_Interrupt_dispatch(uintptr_t mcause, Per_CPU_Control *cpu_self) |
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68 | { |
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69 | /* |
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70 | * Get rid of the most significant bit which indicates if the exception was |
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71 | * caused by an interrupt or not. |
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72 | */ |
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73 | mcause <<= 1; |
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74 | |
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75 | if (mcause == (RISCV_INTERRUPT_TIMER_MACHINE << 1)) { |
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76 | bsp_interrupt_handler_dispatch(RISCV_INTERRUPT_VECTOR_TIMER); |
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77 | } else if (mcause == (RISCV_INTERRUPT_EXTERNAL_MACHINE << 1)) { |
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78 | volatile RISCV_PLIC_hart_regs *plic_hart_regs; |
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79 | uint32_t interrupt_index; |
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80 | |
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81 | plic_hart_regs = cpu_self->cpu_per_cpu.plic_hart_regs; |
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82 | |
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83 | while ((interrupt_index = plic_hart_regs->claim_complete) != 0) { |
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84 | bsp_interrupt_handler_dispatch( |
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85 | RISCV_INTERRUPT_VECTOR_EXTERNAL(interrupt_index) |
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86 | ); |
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87 | |
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88 | plic_hart_regs->claim_complete = interrupt_index; |
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89 | |
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90 | /* |
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91 | * FIXME: It is not clear which fence is necessary here or if a fence is |
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92 | * necessary at all. The goal is that the complete signal is somehow |
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93 | * recognized by the PLIC before the next claim is issued. |
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94 | */ |
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95 | __asm__ volatile ("fence o, i" : : : "memory"); |
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96 | } |
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97 | } else if (mcause == (RISCV_INTERRUPT_SOFTWARE_MACHINE << 1)) { |
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98 | #ifdef RTEMS_SMP |
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99 | /* |
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100 | * Clear the software interrupt on this processor. Synchronization of |
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101 | * inter-processor interrupts is done via Per_CPU_Control::message in |
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102 | * _SMP_Inter_processor_interrupt_handler(). |
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103 | */ |
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104 | *cpu_self->cpu_per_cpu.clint_msip = 0; |
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105 | |
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106 | _SMP_Inter_processor_interrupt_handler(cpu_self); |
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107 | #else |
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108 | bsp_interrupt_handler_dispatch(RISCV_INTERRUPT_VECTOR_SOFTWARE); |
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109 | #endif |
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110 | } else { |
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111 | bsp_fatal(RISCV_FATAL_UNEXPECTED_INTERRUPT_EXCEPTION); |
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112 | } |
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113 | } |
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114 | |
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115 | static void riscv_clint_init(const void *fdt) |
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116 | { |
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117 | volatile RISCV_CLINT_regs *clint; |
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118 | int node; |
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119 | const uint32_t *val; |
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120 | int len; |
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121 | int i; |
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122 | |
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123 | node = fdt_node_offset_by_compatible(fdt, -1, "riscv,clint0"); |
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124 | |
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125 | clint = riscv_fdt_get_address(fdt, node); |
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126 | if (clint == NULL) { |
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127 | bsp_fatal(RISCV_FATAL_NO_CLINT_REG_IN_DEVICE_TREE); |
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128 | } |
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129 | |
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130 | riscv_clint = clint; |
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131 | |
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132 | val = fdt_getprop(fdt, node, "interrupts-extended", &len); |
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133 | |
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134 | for (i = 0; i < len; i += 16) { |
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135 | uint32_t hart_index; |
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136 | Per_CPU_Control *cpu; |
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137 | |
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138 | hart_index = riscv_get_hart_index_by_phandle(fdt32_to_cpu(val[i / 4])); |
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139 | if (hart_index >= rtems_configuration_get_maximum_processors()) { |
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140 | continue; |
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141 | } |
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142 | |
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143 | cpu = _Per_CPU_Get_by_index(hart_index); |
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144 | cpu->cpu_per_cpu.clint_msip = &clint->msip[i / 16]; |
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145 | cpu->cpu_per_cpu.clint_mtimecmp = &clint->mtimecmp[i / 16]; |
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146 | } |
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147 | } |
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148 | |
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149 | static void riscv_plic_init(const void *fdt) |
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150 | { |
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151 | volatile RISCV_PLIC_regs *plic; |
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152 | int node; |
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153 | int i; |
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154 | const uint32_t *val; |
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155 | int len; |
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156 | uint32_t interrupt_index; |
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157 | uint32_t ndev; |
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158 | Per_CPU_Control *cpu; |
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159 | |
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160 | node = fdt_node_offset_by_compatible(fdt, -1, "riscv,plic0"); |
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161 | |
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162 | plic = riscv_fdt_get_address(fdt, node); |
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163 | if (plic == NULL) { |
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164 | #if RISCV_ENABLE_HTIF_SUPPORT != 0 |
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165 | /* Spike platform has HTIF and does not have a PLIC */ |
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166 | return; |
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167 | #else |
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168 | bsp_fatal(RISCV_FATAL_NO_PLIC_REG_IN_DEVICE_TREE); |
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169 | #endif |
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170 | } |
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171 | |
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172 | val = fdt_getprop(fdt, node, "riscv,ndev", &len); |
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173 | if (val == NULL || len != 4) { |
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174 | bsp_fatal(RISCV_FATAL_INVALID_PLIC_NDEV_IN_DEVICE_TREE); |
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175 | } |
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176 | |
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177 | ndev = fdt32_to_cpu(val[0]); |
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178 | if (ndev > RISCV_MAXIMUM_EXTERNAL_INTERRUPTS) { |
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179 | bsp_fatal(RISCV_FATAL_TOO_LARGE_PLIC_NDEV_IN_DEVICE_TREE); |
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180 | } |
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181 | |
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182 | val = fdt_getprop(fdt, node, "interrupts-extended", &len); |
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183 | |
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184 | for (i = 0; i < len; i += 8) { |
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185 | uint32_t hart_index; |
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186 | |
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187 | hart_index = riscv_get_hart_index_by_phandle(fdt32_to_cpu(val[i / 4])); |
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188 | if (hart_index >= rtems_configuration_get_maximum_processors()) { |
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189 | continue; |
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190 | } |
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191 | |
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192 | interrupt_index = fdt32_to_cpu(val[i / 4 + 1]); |
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193 | if (interrupt_index != RISCV_INTERRUPT_EXTERNAL_MACHINE) { |
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194 | continue; |
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195 | } |
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196 | |
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197 | plic->harts[i / 8].priority_threshold = 0; |
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198 | |
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199 | cpu = _Per_CPU_Get_by_index(hart_index); |
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200 | cpu->cpu_per_cpu.plic_hart_regs = &plic->harts[i / 8]; |
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201 | cpu->cpu_per_cpu.plic_m_ie = &plic->enable[i / 8][0]; |
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202 | } |
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203 | |
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204 | cpu = _Per_CPU_Get_by_index(0); |
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205 | |
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206 | for (interrupt_index = 1; interrupt_index <= ndev; ++interrupt_index) { |
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207 | plic->priority[interrupt_index] = 1; |
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208 | riscv_plic_irq_to_cpu[interrupt_index - 1] = cpu->cpu_per_cpu.plic_m_ie; |
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209 | } |
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210 | |
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211 | /* |
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212 | * External M-mode interrupts on secondary processors are enabled in |
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213 | * bsp_start_on_secondary_processor(). |
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214 | */ |
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215 | set_csr(mie, MIP_MEIP); |
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216 | } |
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217 | |
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218 | void bsp_interrupt_facility_initialize(void) |
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219 | { |
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220 | const void *fdt; |
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221 | |
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222 | fdt = bsp_fdt_get(); |
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223 | riscv_clint_init(fdt); |
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224 | riscv_plic_init(fdt); |
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225 | } |
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226 | |
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227 | rtems_status_code bsp_interrupt_get_attributes( |
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228 | rtems_vector_number vector, |
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229 | rtems_interrupt_attributes *attributes |
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230 | ) |
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231 | { |
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232 | return RTEMS_SUCCESSFUL; |
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233 | } |
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234 | |
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235 | rtems_status_code bsp_interrupt_is_pending( |
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236 | rtems_vector_number vector, |
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237 | bool *pending |
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238 | ) |
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239 | { |
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240 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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241 | bsp_interrupt_assert(pending != NULL); |
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242 | *pending = false; |
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243 | return RTEMS_UNSATISFIED; |
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244 | } |
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245 | |
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246 | rtems_status_code bsp_interrupt_raise(rtems_vector_number vector) |
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247 | { |
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248 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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249 | return RTEMS_UNSATISFIED; |
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250 | } |
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251 | |
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252 | #if defined(RTEMS_SMP) |
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253 | rtems_status_code bsp_interrupt_raise_on( |
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254 | rtems_vector_number vector, |
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255 | uint32_t cpu_index |
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256 | ) |
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257 | { |
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258 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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259 | return RTEMS_UNSATISFIED; |
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260 | } |
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261 | #endif |
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262 | |
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263 | rtems_status_code bsp_interrupt_clear(rtems_vector_number vector) |
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264 | { |
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265 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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266 | return RTEMS_UNSATISFIED; |
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267 | } |
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268 | |
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269 | rtems_status_code bsp_interrupt_vector_is_enabled( |
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270 | rtems_vector_number vector, |
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271 | bool *enabled |
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272 | ) |
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273 | { |
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274 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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275 | bsp_interrupt_assert(enabled != NULL); |
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276 | *enabled = false; |
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277 | return RTEMS_UNSATISFIED; |
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278 | } |
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279 | |
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280 | rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector) |
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281 | { |
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282 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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283 | |
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284 | if (RISCV_INTERRUPT_VECTOR_IS_EXTERNAL(vector)) { |
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285 | uint32_t interrupt_index; |
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286 | volatile uint32_t *enable; |
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287 | uint32_t group; |
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288 | uint32_t bit; |
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289 | rtems_interrupt_lock_context lock_context; |
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290 | |
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291 | interrupt_index = RISCV_INTERRUPT_VECTOR_EXTERNAL_TO_INDEX(vector); |
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292 | enable = riscv_plic_irq_to_cpu[interrupt_index - 1]; |
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293 | group = interrupt_index / 32; |
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294 | bit = UINT32_C(1) << (interrupt_index % 32); |
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295 | |
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296 | rtems_interrupt_lock_acquire(&riscv_plic_lock, &lock_context); |
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297 | |
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298 | if (enable != NULL) { |
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299 | enable[group] |= bit; |
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300 | } else { |
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301 | uint32_t cpu_max; |
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302 | uint32_t cpu_index; |
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303 | |
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304 | cpu_max = _SMP_Get_processor_maximum(); |
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305 | |
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306 | for (cpu_index = 0; cpu_index < cpu_max; ++cpu_index) { |
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307 | Per_CPU_Control *cpu; |
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308 | |
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309 | cpu = _Per_CPU_Get_by_index(cpu_index); |
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310 | enable = cpu->cpu_per_cpu.plic_m_ie; |
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311 | |
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312 | if (enable != NULL) { |
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313 | enable[group] |= bit; |
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314 | } |
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315 | } |
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316 | } |
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317 | |
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318 | rtems_interrupt_lock_release(&riscv_plic_lock, &lock_context); |
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319 | } |
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320 | |
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321 | return RTEMS_SUCCESSFUL; |
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322 | } |
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323 | |
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324 | rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector) |
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325 | { |
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326 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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327 | |
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328 | if (RISCV_INTERRUPT_VECTOR_IS_EXTERNAL(vector)) { |
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329 | uint32_t interrupt_index; |
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330 | volatile uint32_t *enable; |
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331 | uint32_t group; |
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332 | uint32_t bit; |
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333 | rtems_interrupt_lock_context lock_context; |
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334 | |
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335 | interrupt_index = RISCV_INTERRUPT_VECTOR_EXTERNAL_TO_INDEX(vector); |
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336 | enable = riscv_plic_irq_to_cpu[interrupt_index - 1]; |
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337 | group = interrupt_index / 32; |
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338 | bit = UINT32_C(1) << (interrupt_index % 32); |
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339 | |
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340 | rtems_interrupt_lock_acquire(&riscv_plic_lock, &lock_context); |
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341 | |
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342 | if (enable != NULL) { |
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343 | enable[group] &= ~bit; |
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344 | } else { |
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345 | uint32_t cpu_max; |
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346 | uint32_t cpu_index; |
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347 | |
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348 | cpu_max = _SMP_Get_processor_maximum(); |
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349 | |
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350 | for (cpu_index = 0; cpu_index < cpu_max; ++cpu_index) { |
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351 | Per_CPU_Control *cpu; |
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352 | |
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353 | cpu = _Per_CPU_Get_by_index(cpu_index); |
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354 | enable = cpu->cpu_per_cpu.plic_m_ie; |
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355 | |
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356 | if (enable != NULL) { |
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357 | enable[group] &= ~bit; |
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358 | } |
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359 | } |
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360 | } |
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361 | |
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362 | rtems_interrupt_lock_release(&riscv_plic_lock, &lock_context); |
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363 | } |
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364 | |
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365 | return RTEMS_SUCCESSFUL; |
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366 | } |
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367 | |
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368 | rtems_status_code bsp_interrupt_set_affinity( |
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369 | rtems_vector_number vector, |
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370 | const Processor_mask *affinity |
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371 | ) |
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372 | { |
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373 | if (RISCV_INTERRUPT_VECTOR_IS_EXTERNAL(vector)) { |
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374 | uint32_t interrupt_index; |
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375 | Processor_mask mask; |
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376 | |
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377 | interrupt_index = RISCV_INTERRUPT_VECTOR_EXTERNAL_TO_INDEX(vector); |
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378 | |
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379 | _Processor_mask_And(&mask, affinity, _SMP_Get_online_processors()); |
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380 | |
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381 | if (_Processor_mask_Is_equal(&mask, _SMP_Get_online_processors())) { |
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382 | riscv_plic_irq_to_cpu[interrupt_index - 1] = NULL; |
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383 | return RTEMS_SUCCESSFUL; |
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384 | } |
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385 | |
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386 | if (_Processor_mask_Count(&mask) == 1) { |
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387 | uint32_t cpu_index; |
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388 | Per_CPU_Control *cpu; |
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389 | |
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390 | cpu_index = _Processor_mask_Find_last_set(&mask) - 1; |
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391 | cpu = _Per_CPU_Get_by_index(cpu_index); |
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392 | riscv_plic_irq_to_cpu[interrupt_index - 1] = cpu->cpu_per_cpu.plic_m_ie; |
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393 | return RTEMS_SUCCESSFUL; |
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394 | } |
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395 | |
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396 | bsp_fatal(RISCV_FATAL_INVALID_INTERRUPT_AFFINITY); |
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397 | } |
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398 | |
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399 | return RTEMS_UNSATISFIED; |
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400 | } |
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401 | |
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402 | rtems_status_code bsp_interrupt_get_affinity( |
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403 | rtems_vector_number vector, |
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404 | Processor_mask *affinity |
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405 | ) |
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406 | { |
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407 | _Processor_mask_Zero(affinity); |
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408 | |
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409 | if (RISCV_INTERRUPT_VECTOR_IS_EXTERNAL(vector)) { |
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410 | uint32_t interrupt_index; |
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411 | volatile uint32_t *enable; |
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412 | |
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413 | interrupt_index = RISCV_INTERRUPT_VECTOR_EXTERNAL_TO_INDEX(vector); |
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414 | enable = riscv_plic_irq_to_cpu[interrupt_index - 1]; |
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415 | |
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416 | if (enable != NULL) { |
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417 | uint32_t cpu_max; |
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418 | uint32_t cpu_index; |
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419 | |
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420 | cpu_max = _SMP_Get_processor_maximum(); |
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421 | |
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422 | for (cpu_index = 0; cpu_index < cpu_max; ++cpu_index) { |
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423 | Per_CPU_Control *cpu; |
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424 | |
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425 | cpu = _Per_CPU_Get_by_index(cpu_index); |
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426 | |
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427 | if (enable == cpu->cpu_per_cpu.plic_m_ie) { |
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428 | _Processor_mask_Set(affinity, cpu_index); |
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429 | break; |
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430 | } |
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431 | } |
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432 | } else { |
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433 | _Processor_mask_Assign(affinity, _SMP_Get_online_processors()); |
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434 | } |
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435 | } |
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436 | |
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437 | return RTEMS_SUCCESSFUL; |
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438 | } |
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