source: rtems/bsps/riscv/riscv/irq/irq.c @ 8db3f0e

Last change on this file since 8db3f0e was 8db3f0e, checked in by Sebastian Huber <sebastian.huber@…>, on Jul 19, 2018 at 10:11:19 AM

riscv: Rework exception handling

Remove _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector()
functions. Applications can install an exception handler via the fatal
error handler to handle synchronous exceptions.

Handle interrupt exceptions via _RISCV_Interrupt_dispatch() which must
be provided by the BSP.

Update #3433.

  • Property mode set to 100644
File size: 2.4 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup riscv_interrupt
5 *
6 * @brief Interrupt support.
7 */
8
9/*
10 * Copyright (c) 2018 embedded brains GmbH
11 *
12 * Copyright (c) 2015 University of York.
13 * Hesham Almatary <hesham@alumni.york.ac.uk>
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 *    notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 *    notice, this list of conditions and the following disclaimer in the
22 *    documentation and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 */
36
37#include <bsp/irq.h>
38#include <bsp/fatal.h>
39#include <bsp/irq-generic.h>
40
41#include <rtems/score/percpu.h>
42
43void _RISCV_Interrupt_dispatch(uintptr_t mcause, Per_CPU_Control *cpu_self)
44{
45  /*
46   * Get rid of the most significant bit which indicates if the exception was
47   * caused by an interrupt or not.
48   */
49  mcause <<= 1;
50
51  if (mcause == (RISCV_INTERRUPT_TIMER_MACHINE << 1)) {
52    bsp_interrupt_handler_dispatch(RISCV_INTERRUPT_VECTOR_TIMER);
53  } else if (mcause == (RISCV_INTERRUPT_EXTERNAL_MACHINE << 1)) {
54    /* TODO: Handle PLIC interrupt */
55  } else if (mcause == (RISCV_INTERRUPT_SOFTWARE_MACHINE << 1)) {
56    bsp_interrupt_handler_dispatch(RISCV_INTERRUPT_VECTOR_SOFTWARE);
57  } else {
58    bsp_fatal(RISCV_FATAL_UNEXPECTED_INTERRUPT_EXCEPTION);
59  }
60}
61
62rtems_status_code bsp_interrupt_facility_initialize(void)
63{
64  return RTEMS_SUCCESSFUL;
65}
66
67void bsp_interrupt_vector_enable(rtems_vector_number vector)
68{
69}
70
71void bsp_interrupt_vector_disable(rtems_vector_number vector)
72{
73}
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