source: rtems/bsps/riscv/riscv/include/bsp/riscv.h @ 26853a06

Last change on this file since 26853a06 was 26853a06, checked in by Alan Cudmore <alan.cudmore@…>, on 03/15/23 at 13:41:53

bsps/riscv: add riscv/kendrytek210 BSP variant source changes

This patch adds support for the Kendryte K210 RISC-V BSP variant.
The SoC uses the existing Interrupt Controller, Timer, and console UART.
It only needs SoC specific initialization and an embedded device tree binary
similar to the polarfire SoC BSP.

Updates #4876
  • Property mode set to 100644
File size: 2.0 KB
Line 
1/*
2 * Copyright (c) 2018 embedded brains GmbH
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 *    notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 *    notice, this list of conditions and the following disclaimer in the
11 *    documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26#ifndef BSP_RISCV_H
27#define BSP_RISCV_H
28
29#include <bsp.h>
30
31#include <rtems/score/cpuimpl.h>
32
33#ifdef __cplusplus
34extern "C" {
35#endif
36
37extern volatile RISCV_CLINT_regs *riscv_clint;
38
39void *riscv_fdt_get_address(const void *fdt, int node);
40
41uint32_t riscv_get_core_frequency(void);
42
43#if RISCV_ENABLE_MPFS_SUPPORT != 0
44extern uint32_t riscv_hart_count;
45#else
46#ifdef RTEMS_SMP
47extern uint32_t riscv_hart_count;
48#else
49#define riscv_hart_count 1
50#endif
51#endif
52
53uint32_t riscv_get_hart_index_by_phandle(uint32_t phandle);
54
55#ifdef RISCV_ENABLE_HTIF_SUPPORT
56void htif_poweroff(void);
57#endif
58
59#if RISCV_ENABLE_KENDRYTE_K210_SUPPORT != 0
60uint32_t k210_get_frequency(void);
61#endif
62
63#ifdef __cplusplus
64}
65#endif
66
67#endif /* BSP_RISCV_H */
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