source: rtems/bsps/riscv/riscv/include/bsp/irq.h @ 8db3f0e

Last change on this file since 8db3f0e was 8db3f0e, checked in by Sebastian Huber <sebastian.huber@…>, on Jul 19, 2018 at 10:11:19 AM

riscv: Rework exception handling

Remove _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector()
functions. Applications can install an exception handler via the fatal
error handler to handle synchronous exceptions.

Handle interrupt exceptions via _RISCV_Interrupt_dispatch() which must
be provided by the BSP.

Update #3433.

  • Property mode set to 100644
File size: 2.0 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup RISCV_IRQ
5 *
6 * @brief Interrupt definitions.
7 */
8
9/*
10 * Copyright (c) 2018 embedded brains GmbH
11 *
12 * Copyright (c) 2015 University of York.
13 * Hesham Almatary <hesham@alumni.york.ac.uk>
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 *    notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 *    notice, this list of conditions and the following disclaimer in the
22 *    documentation and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 */
36
37#ifndef LIBBSP_GENERIC_RISCV_IRQ_H
38#define LIBBSP_GENERIC_RISCV_IRQ_H
39
40#ifndef ASM
41
42#include <bsp.h>
43#include <rtems/irq.h>
44#include <rtems/irq-extension.h>
45
46#define RISCV_INTERRUPT_VECTOR_SOFTWARE 0
47
48#define RISCV_INTERRUPT_VECTOR_TIMER 1
49
50#define RISCV_INTERRUPT_VECTOR_EXTERNAL(x) ((x) + 2)
51
52#define BSP_INTERRUPT_VECTOR_MIN 0
53
54#define BSP_INTERRUPT_VECTOR_MAX RISCV_INTERRUPT_VECTOR_EXTERNAL(RISCV_MAXIMUM_EXTERNAL_INTERRUPTS - 1)
55
56#endif /* ASM */
57
58#endif /* LIBBSP_GENERIC_RISCV_IRQ_H */
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