source: rtems/bsps/riscv/riscv/console/fe310-uart.c @ 26853a06

Last change on this file since 26853a06 was 26853a06, checked in by Alan Cudmore <alan.cudmore@…>, on 03/15/23 at 13:41:53

bsps/riscv: add riscv/kendrytek210 BSP variant source changes

This patch adds support for the Kendryte K210 RISC-V BSP variant.
The SoC uses the existing Interrupt Controller, Timer, and console UART.
It only needs SoC specific initialization and an embedded device tree binary
similar to the polarfire SoC BSP.

Updates #4876

  • Property mode set to 100644
File size: 3.2 KB
Line 
1/*
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2019 Pragnesh Patel <pragnesh.patel@sifive.com>
5 * Copyright (c) 2019 Sachin Ghadi <sachin.ghadi@sifive.com>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <bsp/riscv.h>
30#include <bsp/fe310-uart.h>
31
32#include <assert.h>
33
34int fe310_uart_read(rtems_termios_device_context *base)
35{
36  fe310_uart_context * ctx = (fe310_uart_context*) base;
37  int32_t              rxdata;
38
39  rxdata = ctx->regs->rxdata;
40  if ((rxdata & TXRXREADY) != 0) {
41    return -1;
42  } else {
43    return rxdata & 0xFF;
44  }
45}
46
47static void fe310_uart_write (
48  rtems_termios_device_context  *base,
49  const char                    *buf,
50  size_t                        n
51)
52{
53  fe310_uart_context * ctx = (fe310_uart_context*) base;
54  size_t i;
55
56  ctx->regs->div = (riscv_get_core_frequency() / 115200 - 1) & 0xFFFF;
57  ctx->regs->txctrl |= 1;
58  ctx->regs->rxctrl |= 1;
59
60  for (i = 0; i < n; ++i) {
61    while ((ctx->regs->txdata & TXRXREADY) != 0) {
62      /* Wait */
63    }
64
65    ctx->regs->txdata = buf[i];
66  }
67}
68
69void fe310_console_putchar(rtems_termios_device_context *context, char c)
70{
71  fe310_uart_write(context, &c, 1);
72}
73
74static bool fe310_uart_first_open (
75  rtems_termios_tty             *tty,
76  rtems_termios_device_context  *base,
77  struct termios                *term,
78  rtems_libio_open_close_args_t *args
79)
80{
81  fe310_uart_context * ctx;
82  rtems_status_code sc;
83
84  /* Configure GPIO to be UART */
85
86  sc = rtems_termios_set_initial_baud(tty, B115200);
87  if ( sc != RTEMS_SUCCESSFUL ) {
88    return false;
89  }
90
91  /* Set up a baud rate and enable tx and rx */
92  ctx = (fe310_uart_context *) base;
93  (ctx->regs)->div = riscv_get_core_frequency() / 115200 - 1;
94  (ctx->regs)->txctrl |= 1;
95  (ctx->regs)->rxctrl |= 1;
96  (ctx->regs)->ie = 0;
97  return true;
98};
99
100const rtems_termios_device_handler fe310_uart_handler = {
101  .first_open = fe310_uart_first_open,
102  .write = fe310_uart_write,
103  .poll_read = fe310_uart_read,
104  .mode = TERMIOS_POLLED
105};
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