source: rtems/bsps/riscv/riscv/clock/clockdrv.c @ cfc9573

Last change on this file since cfc9573 was cfc9573, checked in by Sebastian Huber <sebastian.huber@…>, on Jul 27, 2018 at 12:47:17 PM

riscv: Rework CPU counter support

Update #3433.

  • Property mode set to 100644
File size: 4.7 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup bsp_clock
5 *
6 * @brief riscv clock support.
7 */
8
9/*
10 * Copyright (c) 2018 embedded brains GmbH
11 * COPYRIGHT (c) 2015 Hesham Alatary <hesham@alumni.york.ac.uk>
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 *    notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 *    notice, this list of conditions and the following disclaimer in the
20 *    documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 */
34
35#include <bsp/fatal.h>
36#include <bsp/fdt.h>
37#include <bsp/irq.h>
38#include <bsp/riscv.h>
39
40#include <rtems/sysinit.h>
41#include <rtems/timecounter.h>
42#include <rtems/score/cpuimpl.h>
43#include <rtems/score/riscv-utility.h>
44
45#include <libfdt.h>
46
47/* This is defined in dev/clock/clockimpl.h */
48void Clock_isr(void *arg);
49
50typedef struct {
51  struct timecounter base;
52  volatile RISCV_CLINT_regs *clint;
53} riscv_timecounter;
54
55static riscv_timecounter riscv_clock_tc;
56
57static uint32_t riscv_clock_interval;
58
59static void riscv_clock_at_tick(riscv_timecounter *tc)
60{
61  volatile RISCV_CLINT_regs *clint;
62  uint64_t cmp;
63
64  clint = tc->clint;
65
66  cmp = clint->mtimecmp[0].val_64;
67  cmp += riscv_clock_interval;
68
69#if __riscv_xlen == 32
70  clint->mtimecmp[0].val_32[0] = 0xffffffff;
71  clint->mtimecmp[0].val_32[1] = (uint32_t) (cmp >> 32);
72  clint->mtimecmp[0].val_32[0] = (uint32_t) cmp;
73#elif __riscv_xlen == 64
74  clint->mtimecmp[0].val_64 = cmp;
75#endif
76}
77
78static void riscv_clock_handler_install(void)
79{
80  rtems_status_code sc;
81
82  sc = rtems_interrupt_handler_install(
83    RISCV_INTERRUPT_VECTOR_TIMER,
84    "Clock",
85    RTEMS_INTERRUPT_UNIQUE,
86    (rtems_interrupt_handler) Clock_isr,
87    NULL
88  );
89  if (sc != RTEMS_SUCCESSFUL) {
90    bsp_fatal(RISCV_FATAL_CLOCK_IRQ_INSTALL);
91  }
92}
93
94static uint32_t riscv_clock_get_timecount(struct timecounter *base)
95{
96  riscv_timecounter *tc;
97  volatile RISCV_CLINT_regs *clint;
98
99  tc = (riscv_timecounter *) base;
100  clint = tc->clint;
101  return clint->mtime.val_32[0];
102}
103
104static uint32_t riscv_clock_get_timebase_frequency(const void *fdt)
105{
106  int node;
107  const uint32_t *val;
108  int len;
109
110  node = fdt_path_offset(fdt, "/cpus");
111  val = fdt_getprop(fdt, node, "timebase-frequency", &len);
112  if (val == NULL || len < 4) {
113    bsp_fatal(RISCV_FATAL_NO_TIMEBASE_FREQUENCY_IN_DEVICE_TREE);
114  }
115
116  return fdt32_to_cpu(*val);
117}
118
119static void riscv_clock_initialize(void)
120{
121  const char *fdt;
122  riscv_timecounter *tc;
123  uint32_t tb_freq;
124  uint64_t us_per_tick;
125
126  fdt = bsp_fdt_get();
127
128  tc = &riscv_clock_tc;
129  tc->clint = riscv_clint;
130
131  tb_freq = riscv_clock_get_timebase_frequency(fdt);
132  us_per_tick = rtems_configuration_get_microseconds_per_tick();
133  riscv_clock_interval = (uint32_t) ((tb_freq * us_per_tick) / 1000000);
134
135  riscv_clock_at_tick(tc);
136
137  /* Enable mtimer interrupts */
138  set_csr(mie, MIP_MTIP);
139
140  /* Initialize timecounter */
141  tc->base.tc_get_timecount = riscv_clock_get_timecount;
142  tc->base.tc_counter_mask = 0xffffffff;
143  tc->base.tc_frequency = tb_freq;
144  tc->base.tc_quality = RTEMS_TIMECOUNTER_QUALITY_CLOCK_DRIVER;
145  rtems_timecounter_install(&tc->base);
146}
147
148volatile uint32_t _RISCV_Counter_register;
149
150static void riscv_counter_initialize(void)
151{
152  _RISCV_Counter_mutable = &riscv_clint->mtime.val_32[0];
153}
154
155uint32_t _CPU_Counter_frequency( void )
156{
157  return riscv_clock_get_timebase_frequency(bsp_fdt_get());
158}
159
160RTEMS_SYSINIT_ITEM(
161  riscv_counter_initialize,
162  RTEMS_SYSINIT_CPU_COUNTER,
163  RTEMS_SYSINIT_ORDER_FIRST
164);
165
166#define Clock_driver_support_at_tick() riscv_clock_at_tick(&riscv_clock_tc)
167
168#define Clock_driver_support_initialize_hardware() riscv_clock_initialize()
169
170#define Clock_driver_support_install_isr(isr) \
171  riscv_clock_handler_install()
172
173#define CLOCK_DRIVER_USE_ONLY_BOOT_PROCESSOR
174
175#include "../../../shared/dev/clock/clockimpl.h"
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