source: rtems/bsps/riscv/riscv/clock/clockdrv.c @ 8db3f0e

Last change on this file since 8db3f0e was 8db3f0e, checked in by Sebastian Huber <sebastian.huber@…>, on Jul 19, 2018 at 10:11:19 AM

riscv: Rework exception handling

Remove _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector()
functions. Applications can install an exception handler via the fatal
error handler to handle synchronous exceptions.

Handle interrupt exceptions via _RISCV_Interrupt_dispatch() which must
be provided by the BSP.

Update #3433.

  • Property mode set to 100644
File size: 4.1 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup bsp_clock
5 *
6 * @brief riscv clock support.
7 */
8
9/*
10 * Copyright (c) 2018 embedded brains GmbH
11 * COPYRIGHT (c) 2015 Hesham Alatary <hesham@alumni.york.ac.uk>
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 *    notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 *    notice, this list of conditions and the following disclaimer in the
20 *    documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 */
34
35#include <rtems/timecounter.h>
36#include <rtems/score/riscv-utility.h>
37
38#include <bsp.h>
39#include <bsp/fatal.h>
40#include <bsp/fdt.h>
41#include <bsp/irq.h>
42
43#include <dev/irq/clint.h>
44
45#include <libfdt.h>
46
47#define CLINT ((volatile clint_regs *) 0x02000000)
48
49/* This is defined in dev/clock/clockimpl.h */
50void Clock_isr(void *arg);
51
52static struct timecounter riscv_clock_tc;
53
54static uint32_t riscv_clock_interval;
55
56static void riscv_clock_at_tick(void)
57{
58  volatile clint_regs *clint;
59  uint64_t cmp;
60
61  clint = CLINT;
62
63  cmp = clint->mtimecmp[0].val_64;
64  cmp += riscv_clock_interval;
65
66#if __riscv_xlen == 32
67  clint->mtimecmp[0].val_32[0] = 0xffffffff;
68  clint->mtimecmp[0].val_32[1] = (uint32_t) (cmp >> 32);
69  clint->mtimecmp[0].val_32[0] = (uint32_t) cmp;
70#elif __riscv_xlen == 64
71  clint->mtimecmp[0].val_64 = cmp;
72#endif
73}
74
75static void riscv_clock_handler_install(void)
76{
77  rtems_status_code sc;
78
79  sc = rtems_interrupt_handler_install(
80    RISCV_INTERRUPT_VECTOR_TIMER,
81    "Clock",
82    RTEMS_INTERRUPT_UNIQUE,
83    (rtems_interrupt_handler) Clock_isr,
84    NULL
85  );
86  if (sc != RTEMS_SUCCESSFUL) {
87    bsp_fatal(RISCV_FATAL_CLOCK_IRQ_INSTALL);
88  }
89}
90
91static uint32_t riscv_clock_get_timecount(struct timecounter *tc)
92{
93  volatile clint_regs *clint;
94
95  clint = CLINT;
96  return clint->mtime.val_32[0];
97}
98
99static uint32_t riscv_clock_get_timebase_frequency(const void *fdt)
100{
101  int node;
102  const uint32_t *val;
103  int len;
104
105  node = fdt_path_offset(fdt, "/cpus");
106  val = fdt_getprop(fdt, node, "timebase-frequency", &len);
107  if (val == NULL || len < 4) {
108    bsp_fatal(RISCV_FATAL_NO_TIMEBASE_FREQUENCY_IN_DEVICE_TREE);
109  }
110
111  return fdt32_to_cpu(*val);
112}
113
114static void riscv_clock_initialize(void)
115{
116  const char *fdt;
117  uint32_t tb_freq;
118  uint64_t us_per_tick;
119
120  fdt = bsp_fdt_get();
121  tb_freq = riscv_clock_get_timebase_frequency(fdt);
122  us_per_tick = rtems_configuration_get_microseconds_per_tick();
123  riscv_clock_interval = (uint32_t) ((tb_freq * us_per_tick) / 1000000);
124
125  riscv_clock_at_tick();
126
127  /* Enable mtimer interrupts */
128  set_csr(mie, MIP_MTIP);
129
130  /* Initialize timecounter */
131  riscv_clock_tc.tc_get_timecount = riscv_clock_get_timecount;
132  riscv_clock_tc.tc_counter_mask = 0xffffffff;
133  riscv_clock_tc.tc_frequency = tb_freq;
134  riscv_clock_tc.tc_quality = RTEMS_TIMECOUNTER_QUALITY_CLOCK_DRIVER;
135  rtems_timecounter_install(&riscv_clock_tc);
136}
137
138uint32_t _CPU_Counter_frequency( void )
139{
140  return riscv_clock_get_timebase_frequency(bsp_fdt_get());
141}
142
143#define Clock_driver_support_at_tick() riscv_clock_at_tick()
144
145#define Clock_driver_support_initialize_hardware() riscv_clock_initialize()
146
147#define Clock_driver_support_install_isr(isr) \
148  riscv_clock_handler_install()
149
150#include "../../../shared/dev/clock/clockimpl.h"
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