1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup bsp_clock |
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5 | * |
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6 | * @brief riscv clock support. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2018 embedded brains GmbH |
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11 | * COPYRIGHT (c) 2015 Hesham Alatary <hesham@alumni.york.ac.uk> |
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12 | * |
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13 | * Redistribution and use in source and binary forms, with or without |
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14 | * modification, are permitted provided that the following conditions |
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15 | * are met: |
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16 | * 1. Redistributions of source code must retain the above copyright |
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17 | * notice, this list of conditions and the following disclaimer. |
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18 | * 2. Redistributions in binary form must reproduce the above copyright |
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19 | * notice, this list of conditions and the following disclaimer in the |
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20 | * documentation and/or other materials provided with the distribution. |
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21 | * |
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22 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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23 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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25 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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28 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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29 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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30 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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31 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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32 | * SUCH DAMAGE. |
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33 | */ |
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34 | |
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35 | #include <rtems/timecounter.h> |
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36 | #include <rtems/score/riscv-utility.h> |
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37 | |
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38 | #include <bsp.h> |
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39 | #include <bsp/fatal.h> |
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40 | #include <bsp/fdt.h> |
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41 | #include <bsp/irq.h> |
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42 | |
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43 | #include <dev/irq/clint.h> |
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44 | |
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45 | #include <libfdt.h> |
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46 | |
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47 | #define CLINT ((volatile clint_regs *) 0x02000000) |
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48 | |
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49 | /* This is defined in dev/clock/clockimpl.h */ |
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50 | void Clock_isr(void *arg); |
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51 | |
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52 | static struct timecounter riscv_clock_tc; |
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53 | |
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54 | static uint32_t riscv_clock_interval; |
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55 | |
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56 | static void riscv_clock_at_tick(void) |
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57 | { |
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58 | volatile clint_regs *clint; |
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59 | uint64_t cmp; |
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60 | |
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61 | clint = CLINT; |
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62 | |
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63 | cmp = clint->mtimecmp[0].val_64; |
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64 | cmp += riscv_clock_interval; |
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65 | |
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66 | #if __riscv_xlen == 32 |
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67 | clint->mtimecmp[0].val_32[0] = 0xffffffff; |
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68 | clint->mtimecmp[0].val_32[1] = (uint32_t) (cmp >> 32); |
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69 | clint->mtimecmp[0].val_32[0] = (uint32_t) cmp; |
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70 | #elif __riscv_xlen == 64 |
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71 | clint->mtimecmp[0].val_64 = cmp; |
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72 | #endif |
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73 | } |
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74 | |
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75 | static void riscv_clock_handler_install(void) |
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76 | { |
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77 | rtems_status_code sc; |
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78 | |
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79 | sc = rtems_interrupt_handler_install( |
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80 | RISCV_INTERRUPT_VECTOR_TIMER, |
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81 | "Clock", |
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82 | RTEMS_INTERRUPT_UNIQUE, |
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83 | (rtems_interrupt_handler) Clock_isr, |
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84 | NULL |
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85 | ); |
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86 | if (sc != RTEMS_SUCCESSFUL) { |
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87 | bsp_fatal(RISCV_FATAL_CLOCK_IRQ_INSTALL); |
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88 | } |
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89 | } |
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90 | |
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91 | static uint32_t riscv_clock_get_timecount(struct timecounter *tc) |
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92 | { |
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93 | volatile clint_regs *clint; |
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94 | |
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95 | clint = CLINT; |
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96 | return clint->mtime.val_32[0]; |
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97 | } |
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98 | |
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99 | static uint32_t riscv_clock_get_timebase_frequency(const void *fdt) |
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100 | { |
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101 | int node; |
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102 | const uint32_t *val; |
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103 | int len; |
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104 | |
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105 | node = fdt_path_offset(fdt, "/cpus"); |
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106 | val = fdt_getprop(fdt, node, "timebase-frequency", &len); |
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107 | if (val == NULL || len < 4) { |
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108 | bsp_fatal(RISCV_FATAL_NO_TIMEBASE_FREQUENCY_IN_DEVICE_TREE); |
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109 | } |
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110 | |
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111 | return fdt32_to_cpu(*val); |
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112 | } |
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113 | |
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114 | static void riscv_clock_initialize(void) |
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115 | { |
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116 | const char *fdt; |
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117 | uint32_t tb_freq; |
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118 | uint64_t us_per_tick; |
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119 | |
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120 | fdt = bsp_fdt_get(); |
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121 | tb_freq = riscv_clock_get_timebase_frequency(fdt); |
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122 | us_per_tick = rtems_configuration_get_microseconds_per_tick(); |
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123 | riscv_clock_interval = (uint32_t) ((tb_freq * us_per_tick) / 1000000); |
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124 | |
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125 | riscv_clock_at_tick(); |
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126 | |
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127 | /* Enable mtimer interrupts */ |
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128 | set_csr(mie, MIP_MTIP); |
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129 | |
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130 | /* Initialize timecounter */ |
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131 | riscv_clock_tc.tc_get_timecount = riscv_clock_get_timecount; |
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132 | riscv_clock_tc.tc_counter_mask = 0xffffffff; |
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133 | riscv_clock_tc.tc_frequency = tb_freq; |
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134 | riscv_clock_tc.tc_quality = RTEMS_TIMECOUNTER_QUALITY_CLOCK_DRIVER; |
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135 | rtems_timecounter_install(&riscv_clock_tc); |
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136 | } |
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137 | |
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138 | uint32_t _CPU_Counter_frequency( void ) |
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139 | { |
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140 | return riscv_clock_get_timebase_frequency(bsp_fdt_get()); |
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141 | } |
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142 | |
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143 | #define Clock_driver_support_at_tick() riscv_clock_at_tick() |
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144 | |
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145 | #define Clock_driver_support_initialize_hardware() riscv_clock_initialize() |
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146 | |
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147 | #define Clock_driver_support_install_isr(isr) \ |
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148 | riscv_clock_handler_install() |
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149 | |
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150 | #include "../../../shared/dev/clock/clockimpl.h" |
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