1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup RTEMSDriverClockImpl |
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5 | * |
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6 | * @brief This source file contains the implementation of the riscv Clock |
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7 | * Driver. |
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8 | */ |
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9 | |
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10 | /* |
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11 | * Copyright (c) 2018 embedded brains GmbH |
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12 | * COPYRIGHT (c) 2015 Hesham Alatary <hesham@alumni.york.ac.uk> |
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13 | * |
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14 | * Redistribution and use in source and binary forms, with or without |
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15 | * modification, are permitted provided that the following conditions |
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16 | * are met: |
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17 | * 1. Redistributions of source code must retain the above copyright |
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18 | * notice, this list of conditions and the following disclaimer. |
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19 | * 2. Redistributions in binary form must reproduce the above copyright |
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20 | * notice, this list of conditions and the following disclaimer in the |
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21 | * documentation and/or other materials provided with the distribution. |
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22 | * |
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23 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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24 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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25 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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26 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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27 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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28 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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29 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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30 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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31 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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32 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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33 | * SUCH DAMAGE. |
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34 | */ |
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35 | |
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36 | #include <bsp/fatal.h> |
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37 | #include <bsp/fdt.h> |
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38 | #include <bsp/irq.h> |
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39 | #include <bsp/riscv.h> |
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40 | |
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41 | #include <rtems/sysinit.h> |
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42 | #include <rtems/timecounter.h> |
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43 | #include <rtems/score/cpuimpl.h> |
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44 | #include <rtems/score/riscv-utility.h> |
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45 | #include <rtems/score/smpimpl.h> |
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46 | |
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47 | #include <libfdt.h> |
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48 | |
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49 | /* This is defined in dev/clock/clockimpl.h */ |
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50 | void Clock_isr(void *arg); |
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51 | |
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52 | typedef struct { |
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53 | struct timecounter base; |
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54 | volatile RISCV_CLINT_regs *clint; |
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55 | uint32_t interval; |
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56 | } riscv_timecounter; |
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57 | |
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58 | static riscv_timecounter riscv_clock_tc; |
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59 | |
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60 | static void riscv_clock_write_mtimecmp( |
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61 | volatile RISCV_CLINT_timer_reg *mtimecmp, |
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62 | uint64_t value |
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63 | ) |
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64 | { |
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65 | #if __riscv_xlen == 32 |
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66 | mtimecmp->val_32[0] = 0xffffffff; |
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67 | mtimecmp->val_32[1] = (uint32_t) (value >> 32); |
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68 | mtimecmp->val_32[0] = (uint32_t) value; |
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69 | #elif __riscv_xlen == 64 |
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70 | mtimecmp->val_64 = value; |
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71 | #endif |
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72 | } |
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73 | |
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74 | static uint64_t riscv_clock_read_mtime(volatile RISCV_CLINT_timer_reg *mtime) |
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75 | { |
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76 | #if __riscv_xlen == 32 |
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77 | uint32_t low; |
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78 | uint32_t high_0; |
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79 | uint32_t high_1; |
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80 | |
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81 | do { |
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82 | high_0 = mtime->val_32[1]; |
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83 | low = mtime->val_32[0]; |
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84 | high_1 = mtime->val_32[1]; |
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85 | } while (high_0 != high_1); |
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86 | |
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87 | return (((uint64_t) high_0) << 32) | low; |
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88 | #elif __riscv_xlen == 64 |
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89 | return mtime->val_64; |
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90 | #endif |
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91 | } |
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92 | |
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93 | static void riscv_clock_at_tick(riscv_timecounter *tc) |
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94 | { |
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95 | volatile RISCV_CLINT_regs *clint; |
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96 | uint64_t value; |
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97 | uint32_t cpu = rtems_scheduler_get_processor(); |
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98 | |
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99 | cpu = _RISCV_Map_cpu_index_to_hardid(cpu); |
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100 | |
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101 | clint = tc->clint; |
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102 | |
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103 | value = clint->mtimecmp[cpu].val_64; |
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104 | value += tc->interval; |
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105 | |
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106 | riscv_clock_write_mtimecmp(&clint->mtimecmp[cpu], value); |
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107 | } |
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108 | |
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109 | static void riscv_clock_handler_install(void) |
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110 | { |
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111 | rtems_status_code sc; |
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112 | |
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113 | sc = rtems_interrupt_handler_install( |
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114 | RISCV_INTERRUPT_VECTOR_TIMER, |
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115 | "Clock", |
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116 | RTEMS_INTERRUPT_UNIQUE, |
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117 | (rtems_interrupt_handler) Clock_isr, |
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118 | NULL |
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119 | ); |
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120 | if (sc != RTEMS_SUCCESSFUL) { |
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121 | bsp_fatal(RISCV_FATAL_CLOCK_IRQ_INSTALL); |
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122 | } |
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123 | } |
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124 | |
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125 | static uint32_t riscv_clock_get_timecount(struct timecounter *base) |
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126 | { |
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127 | riscv_timecounter *tc; |
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128 | volatile RISCV_CLINT_regs *clint; |
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129 | |
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130 | tc = (riscv_timecounter *) base; |
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131 | clint = tc->clint; |
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132 | return clint->mtime.val_32[0]; |
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133 | } |
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134 | |
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135 | static uint32_t riscv_clock_get_timebase_frequency(const void *fdt) |
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136 | { |
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137 | int node; |
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138 | const fdt32_t *val; |
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139 | int len=0; |
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140 | |
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141 | node = fdt_path_offset(fdt, "/cpus"); |
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142 | |
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143 | val = (fdt32_t *) fdt_getprop(fdt, node, "timebase-frequency", &len); |
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144 | |
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145 | if (val == NULL || len < 4) { |
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146 | int cpu0 = fdt_subnode_offset(fdt, node, "cpu@0"); |
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147 | val = (fdt32_t *) fdt_getprop(fdt, cpu0, "timebase-frequency", &len); |
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148 | |
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149 | if (val == NULL || len < 4) { |
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150 | bsp_fatal(RISCV_FATAL_NO_TIMEBASE_FREQUENCY_IN_DEVICE_TREE); |
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151 | } |
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152 | } |
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153 | return fdt32_to_cpu(*val); |
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154 | } |
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155 | |
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156 | static void riscv_clock_clint_init( |
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157 | volatile RISCV_CLINT_regs *clint, |
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158 | uint64_t cmpval, |
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159 | uint32_t cpu |
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160 | ) |
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161 | { |
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162 | riscv_clock_write_mtimecmp( |
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163 | &clint->mtimecmp[cpu], |
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164 | cmpval |
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165 | ); |
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166 | |
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167 | /* Enable mtimer interrupts */ |
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168 | set_csr(mie, MIP_MTIP); |
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169 | } |
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170 | |
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171 | #if defined(RTEMS_SMP) && !defined(CLOCK_DRIVER_USE_ONLY_BOOT_PROCESSOR) |
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172 | static void riscv_clock_secondary_action(void *arg) |
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173 | { |
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174 | volatile RISCV_CLINT_regs *clint = riscv_clint; |
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175 | uint64_t *cmpval = arg; |
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176 | uint32_t cpu = _CPU_SMP_Get_current_processor(); |
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177 | |
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178 | cpu = _RISCV_Map_cpu_index_to_hardid(cpu); |
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179 | |
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180 | riscv_clock_clint_init(clint, *cmpval, cpu); |
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181 | } |
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182 | #endif |
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183 | |
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184 | static void riscv_clock_secondary_initialization( |
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185 | volatile RISCV_CLINT_regs *clint, |
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186 | uint64_t cmpval, |
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187 | uint32_t interval |
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188 | ) |
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189 | { |
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190 | #if defined(RTEMS_SMP) && !defined(CLOCK_DRIVER_USE_ONLY_BOOT_PROCESSOR) |
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191 | _SMP_Othercast_action(riscv_clock_secondary_action, &cmpval); |
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192 | |
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193 | if (cmpval - riscv_clock_read_mtime(&clint->mtime) >= interval) { |
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194 | bsp_fatal(RISCV_FATAL_CLOCK_SMP_INIT); |
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195 | } |
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196 | #endif |
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197 | } |
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198 | |
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199 | static void riscv_clock_initialize(void) |
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200 | { |
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201 | const char *fdt; |
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202 | riscv_timecounter *tc; |
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203 | volatile RISCV_CLINT_regs *clint; |
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204 | uint32_t tb_freq; |
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205 | uint64_t us_per_tick; |
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206 | uint32_t interval; |
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207 | uint64_t cmpval; |
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208 | |
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209 | fdt = bsp_fdt_get(); |
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210 | tb_freq = riscv_clock_get_timebase_frequency(fdt); |
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211 | us_per_tick = rtems_configuration_get_microseconds_per_tick(); |
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212 | interval = (uint32_t) ((tb_freq * us_per_tick) / 1000000); |
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213 | clint = riscv_clint; |
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214 | tc = &riscv_clock_tc; |
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215 | |
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216 | tc->clint = clint; |
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217 | tc->interval = interval; |
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218 | |
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219 | cmpval = riscv_clock_read_mtime(&clint->mtime); |
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220 | cmpval += interval; |
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221 | |
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222 | riscv_clock_clint_init(clint, cmpval, RISCV_BOOT_HARTID); |
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223 | riscv_clock_secondary_initialization(clint, cmpval, interval); |
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224 | |
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225 | /* Initialize timecounter */ |
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226 | tc->base.tc_get_timecount = riscv_clock_get_timecount; |
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227 | tc->base.tc_counter_mask = 0xffffffff; |
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228 | tc->base.tc_frequency = tb_freq; |
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229 | tc->base.tc_quality = RTEMS_TIMECOUNTER_QUALITY_CLOCK_DRIVER; |
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230 | rtems_timecounter_install(&tc->base); |
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231 | } |
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232 | |
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233 | volatile uint32_t _RISCV_Counter_register; |
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234 | |
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235 | static void riscv_counter_initialize(void) |
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236 | { |
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237 | _RISCV_Counter_mutable = &riscv_clint->mtime.val_32[0]; |
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238 | } |
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239 | |
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240 | uint32_t _CPU_Counter_frequency( void ) |
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241 | { |
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242 | return riscv_clock_get_timebase_frequency(bsp_fdt_get()); |
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243 | } |
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244 | |
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245 | CPU_Counter_ticks _CPU_Counter_read( void ) |
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246 | { |
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247 | return *_RISCV_Counter; |
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248 | } |
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249 | |
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250 | RTEMS_SYSINIT_ITEM( |
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251 | riscv_counter_initialize, |
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252 | RTEMS_SYSINIT_CPU_COUNTER, |
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253 | RTEMS_SYSINIT_ORDER_FIRST |
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254 | ); |
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255 | |
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256 | #define Clock_driver_support_at_tick() riscv_clock_at_tick(&riscv_clock_tc) |
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257 | |
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258 | #define Clock_driver_support_initialize_hardware() riscv_clock_initialize() |
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259 | |
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260 | #define Clock_driver_support_install_isr(isr) \ |
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261 | riscv_clock_handler_install() |
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262 | |
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263 | #include "../../../shared/dev/clock/clockimpl.h" |
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