1 | /* |
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2 | * Copyright (c) 2018 embedded brains GmbH |
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3 | * |
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4 | * Redistribution and use in source and binary forms, with or without |
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5 | * modification, are permitted provided that the following conditions |
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6 | * are met: |
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7 | * 1. Redistributions of source code must retain the above copyright |
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8 | * notice, this list of conditions and the following disclaimer. |
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9 | * 2. Redistributions in binary form must reproduce the above copyright |
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10 | * notice, this list of conditions and the following disclaimer in the |
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11 | * documentation and/or other materials provided with the distribution. |
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12 | * |
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13 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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14 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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15 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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16 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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17 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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18 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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19 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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20 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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21 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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22 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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23 | * SUCH DAMAGE. |
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24 | */ |
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25 | |
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26 | #include <bsp/bootcard.h> |
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27 | #include <bsp/irq.h> |
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28 | #include <amba.h> |
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29 | |
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30 | #include <rtems/score/riscv-utility.h> |
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31 | #include <rtems/score/smpimpl.h> |
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32 | |
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33 | static rtems_isr bsp_inter_processor_interrupt( void *v ) |
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34 | { |
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35 | _SMP_Inter_processor_interrupt_handler(_Per_CPU_Get()); |
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36 | } |
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37 | |
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38 | void bsp_start_on_secondary_processor(Per_CPU_Control *cpu_self) |
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39 | { |
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40 | uint32_t cpu_index_self; |
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41 | |
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42 | cpu_index_self = _Per_CPU_Get_index(cpu_self); |
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43 | GRLIB_IrqCtrl_Regs->mask[cpu_index_self] |= 1U << GRLIB_mp_irq; |
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44 | |
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45 | if ( |
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46 | cpu_index_self < rtems_configuration_get_maximum_processors() |
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47 | && _SMP_Should_start_processor(cpu_index_self) |
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48 | ) { |
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49 | set_csr(mie, MIP_MEIP); |
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50 | _SMP_Start_multitasking_on_secondary_processor(cpu_self); |
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51 | } else { |
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52 | _CPU_Thread_Idle_body(0); |
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53 | } |
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54 | } |
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55 | |
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56 | uint32_t _CPU_SMP_Initialize(void) |
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57 | { |
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58 | if ( rtems_configuration_get_maximum_processors() > 1 ) { |
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59 | GRLIB_Cpu_Unmask_interrupt(GRLIB_mp_irq, _CPU_SMP_Get_current_processor()); |
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60 | |
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61 | rtems_interrupt_handler_install( |
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62 | GRLIB_mp_irq, |
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63 | "IPI", |
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64 | RTEMS_INTERRUPT_SHARED, |
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65 | bsp_inter_processor_interrupt, |
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66 | NULL |
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67 | ); |
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68 | |
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69 | } |
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70 | |
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71 | return grlib_get_cpu_count(GRLIB_IrqCtrl_Regs); |
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72 | } |
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73 | |
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74 | bool _CPU_SMP_Start_processor(uint32_t cpu_index) |
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75 | { |
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76 | GRLIB_IrqCtrl_Regs->mpstat = 1U << cpu_index; |
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77 | |
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78 | return true; |
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79 | } |
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80 | |
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81 | void _CPU_SMP_Finalize_initialization(uint32_t cpu_count) |
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82 | { |
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83 | (void) cpu_count; |
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84 | // set_csr(mie, MIP_MSIP); |
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85 | } |
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86 | |
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87 | void _CPU_SMP_Prepare_start_multitasking(void) |
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88 | { |
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89 | /* Do nothing */ |
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90 | } |
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91 | |
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92 | void _CPU_SMP_Send_interrupt(uint32_t target_processor_index) |
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93 | { |
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94 | |
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95 | GRLIB_IrqCtrl_Regs->force[target_processor_index] = 1 << GRLIB_mp_irq; |
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96 | |
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97 | } |
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