1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup riscv_interrupt |
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5 | * |
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6 | * @brief Interrupt support. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2018 embedded brains GmbH |
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11 | * |
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12 | * Copyright (c) 2015 University of York. |
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13 | * Hesham Almatary <hesham@alumni.york.ac.uk> |
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14 | * |
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15 | * Redistribution and use in source and binary forms, with or without |
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16 | * modification, are permitted provided that the following conditions |
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17 | * are met: |
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18 | * 1. Redistributions of source code must retain the above copyright |
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19 | * notice, this list of conditions and the following disclaimer. |
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20 | * 2. Redistributions in binary form must reproduce the above copyright |
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21 | * notice, this list of conditions and the following disclaimer in the |
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22 | * documentation and/or other materials provided with the distribution. |
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23 | * |
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24 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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25 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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27 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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30 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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31 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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32 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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33 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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34 | * SUCH DAMAGE. |
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35 | */ |
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36 | |
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37 | #include <bsp/irq.h> |
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38 | #include <bsp/fatal.h> |
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39 | #include <bsp/irq-generic.h> |
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40 | #include <amba.h> |
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41 | |
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42 | #include <rtems/score/percpu.h> |
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43 | #include <rtems/score/riscv-utility.h> |
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44 | #include <rtems/score/smpimpl.h> |
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45 | |
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46 | rtems_interrupt_lock GRLIB_IrqCtrl_Lock; |
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47 | |
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48 | #if defined(RTEMS_SMP) |
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49 | /* Interrupt to CPU map. Default to CPU0 since in BSS. */ |
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50 | const unsigned char GRLIB_irq_to_cpu[32] __attribute__((weak)); |
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51 | |
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52 | /* On SMP use map table above relative to SMP Boot CPU (normally CPU0) */ |
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53 | static inline int bsp_irq_cpu(int irq) |
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54 | { |
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55 | /* protect from bad user configuration, default to boot cpu */ |
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56 | if (rtems_configuration_get_maximum_processors() <= GRLIB_irq_to_cpu[irq]) |
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57 | return GRLIB_Cpu_Index; |
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58 | else |
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59 | return GRLIB_Cpu_Index + GRLIB_irq_to_cpu[irq]; |
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60 | } |
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61 | #else |
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62 | /* when not SMP the local CPU is returned */ |
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63 | static inline int bsp_irq_cpu(int irq) |
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64 | { |
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65 | return read_csr(mhartid); |
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66 | } |
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67 | #endif |
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68 | |
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69 | void _RISCV_Interrupt_dispatch(uintptr_t mcause, Per_CPU_Control *cpu_self) |
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70 | { |
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71 | if (mcause & 0x80000000) { |
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72 | |
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73 | bsp_interrupt_handler_dispatch(mcause & 0xf); |
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74 | |
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75 | } else { |
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76 | bsp_fatal(RISCV_FATAL_UNEXPECTED_INTERRUPT_EXCEPTION); |
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77 | } |
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78 | } |
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79 | |
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80 | rtems_status_code bsp_interrupt_facility_initialize(void) |
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81 | { |
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82 | |
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83 | /* |
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84 | * External M-mode interrupts on secondary processors are enabled in |
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85 | * bsp_start_on_secondary_processor(). |
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86 | */ |
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87 | set_csr(mie, MIP_MEIP); |
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88 | |
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89 | return RTEMS_SUCCESSFUL; |
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90 | } |
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91 | |
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92 | void bsp_interrupt_vector_enable(rtems_vector_number vector) |
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93 | { |
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94 | int irq = (int)vector; |
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95 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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96 | GRLIB_Cpu_Unmask_interrupt(irq, bsp_irq_cpu(irq)); |
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97 | } |
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98 | |
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99 | void bsp_interrupt_vector_disable(rtems_vector_number vector) |
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100 | { |
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101 | int irq = (int)vector; |
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102 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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103 | GRLIB_Cpu_Mask_interrupt(irq, bsp_irq_cpu(irq)); |
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104 | } |
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105 | |
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106 | void bsp_interrupt_get_affinity( |
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107 | rtems_vector_number vector, |
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108 | Processor_mask *affinity |
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109 | ) |
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110 | { |
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111 | uint32_t cpu_count = rtems_get_processor_count(); |
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112 | uint32_t cpu_index; |
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113 | |
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114 | _Processor_mask_Zero(affinity); |
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115 | |
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116 | for (cpu_index = 0; cpu_index < cpu_count; ++cpu_index) { |
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117 | if (!BSP_Cpu_Is_interrupt_masked(vector, cpu_index)) { |
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118 | _Processor_mask_Set(affinity, cpu_index); |
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119 | } |
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120 | } |
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121 | } |
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122 | |
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123 | void bsp_interrupt_set_affinity( |
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124 | rtems_vector_number vector, |
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125 | const Processor_mask *affinity |
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126 | ) |
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127 | { |
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128 | uint32_t unmasked = 0; |
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129 | uint32_t cpu_count = rtems_get_processor_count(); |
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130 | uint32_t cpu_index; |
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131 | |
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132 | for (cpu_index = 0; cpu_index < cpu_count; ++cpu_index) { |
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133 | if (_Processor_mask_Is_set(affinity, cpu_index)) { |
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134 | GRLIB_Cpu_Unmask_interrupt(vector, cpu_index); |
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135 | ++unmasked; |
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136 | } |
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137 | } |
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138 | |
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139 | if (unmasked > 1) { |
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140 | GRLIB_Enable_interrupt_broadcast(vector); |
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141 | } else { |
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142 | GRLIB_Disable_interrupt_broadcast(vector); |
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143 | } |
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144 | } |
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