1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup RTEMSBSPsPowerPCVirtex5MMU |
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5 | * |
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6 | * @brief Implementation of routines to manipulate the PPC 440 MMU. |
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7 | * |
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8 | * Since this is a real-time OS we want to stay away from |
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9 | * software TLB replacement. |
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10 | */ |
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11 | /* |
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12 | * Authorship |
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13 | * ---------- |
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14 | * This software was created by |
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15 | * Till Straumann <strauman@slac.stanford.edu>, 2005-2007, |
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16 | * Stanford Linear Accelerator Center, Stanford University. |
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17 | * and was transcribed for the PPC 440 by |
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18 | * R. Claus <claus@slac.stanford.edu>, 2012, |
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19 | * Stanford Linear Accelerator Center, Stanford University, |
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20 | * |
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21 | * Acknowledgement of sponsorship |
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22 | * ------------------------------ |
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23 | * This software was produced by |
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24 | * the Stanford Linear Accelerator Center, Stanford University, |
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25 | * under Contract DE-AC03-76SFO0515 with the Department of Energy. |
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26 | * |
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27 | * Government disclaimer of liability |
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28 | * ---------------------------------- |
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29 | * Neither the United States nor the United States Department of Energy, |
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30 | * nor any of their employees, makes any warranty, express or implied, or |
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31 | * assumes any legal liability or responsibility for the accuracy, |
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32 | * completeness, or usefulness of any data, apparatus, product, or process |
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33 | * disclosed, or represents that its use would not infringe privately owned |
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34 | * rights. |
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35 | * |
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36 | * Stanford disclaimer of liability |
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37 | * -------------------------------- |
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38 | * Stanford University makes no representations or warranties, express or |
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39 | * implied, nor assumes any liability for the use of this software. |
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40 | * |
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41 | * Stanford disclaimer of copyright |
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42 | * -------------------------------- |
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43 | * Stanford University, owner of the copyright, hereby disclaims its |
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44 | * copyright and all other rights in this software. Hence, anyone may |
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45 | * freely use it for any purpose without restriction. |
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46 | * |
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47 | * Maintenance of notices |
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48 | * ---------------------- |
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49 | * In the interest of clarity regarding the origin and status of this |
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50 | * SLAC software, this and all the preceding Stanford University notices |
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51 | * are to remain affixed to any copy or derivative of this software made |
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52 | * or distributed by the recipient and are to be affixed to any copy of |
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53 | * software made or distributed by the recipient that contains a copy or |
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54 | * derivative of this software. |
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55 | * |
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56 | * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 |
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57 | */ |
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58 | |
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59 | /* 440 MSR definitions; note that there are *substantial* differences |
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60 | * compared to classic powerpc; in particular, IS/DS are *different* |
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61 | * from IR/DR; the ppc440 MMU cannot be switched off! |
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62 | * |
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63 | * Also: To disable/enable all external interrupts, CE and EE must both be |
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64 | * controlled. |
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65 | */ |
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66 | #include <rtems.h> |
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67 | #include <rtems/bspIo.h> |
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68 | #include <rtems/powerpc/powerpc.h> |
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69 | #include <inttypes.h> |
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70 | #include <stdio.h> |
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71 | |
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72 | #include <bsp/mmu.h> |
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73 | |
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74 | |
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75 | #ifdef DEBUG |
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76 | #define STATIC |
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77 | #else |
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78 | #define STATIC static |
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79 | #endif |
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80 | |
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81 | |
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82 | bsp_tlb_entry_t* bsp_mmu_cache = 0; |
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83 | |
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84 | |
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85 | /* Since it is likely that these routines are used during |
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86 | * early initialization when stdio is not available yet |
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87 | * we provide a helper that resorts to 'printk()' |
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88 | */ |
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89 | static void |
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90 | myprintf(FILE *f, char *fmt, ...) |
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91 | { |
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92 | va_list ap; |
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93 | va_start(ap, fmt); |
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94 | |
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95 | if (!f || !_impure_ptr->__sdidinit) { |
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96 | /* Might be called at an early stage when stdio is not yet initialized. */ |
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97 | vprintk(fmt,ap); |
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98 | } else { |
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99 | vfprintf(f,fmt,ap); |
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100 | } |
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101 | va_end(ap); |
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102 | } |
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103 | |
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104 | |
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105 | void |
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106 | bsp_mmu_dump_cache(FILE *f) |
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107 | { |
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108 | bsp_tlb_idx_t idx; |
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109 | if ( !bsp_mmu_cache ) { |
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110 | myprintf(stderr,"MMU TLB cache not initialized\n"); |
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111 | return; |
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112 | } |
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113 | for ( idx=0; idx<NTLBS; idx++ ) { |
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114 | bsp_tlb_entry_t *tlb = bsp_mmu_cache + idx; |
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115 | if ( !tlb->w0.v ) |
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116 | continue; |
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117 | myprintf(f, "#%2i: EA 0x%08x .. 0x%08x, TID 0x%03x, TS %i\n", |
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118 | idx, |
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119 | tlb->w0.epn<<10, |
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120 | (tlb->w0.epn<<10) + (1024<<(2*tlb->w0.size))-1, |
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121 | tlb->id.tid, |
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122 | tlb->w0.ts); |
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123 | myprintf(f, " PA 0x%08"PRIx32", U0-3 0x%01x, WIMGE 0x%02x, PERM 0x%03x\n", |
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124 | tlb->w1.rpn<<10, |
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125 | tlb->w2.att, |
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126 | tlb->w2.wimge, |
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127 | tlb->w2.perm); |
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128 | } |
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129 | } |
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130 | |
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131 | static void |
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132 | fetch(bsp_tlb_idx_t key, bsp_tlb_entry_t* tlb) |
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133 | { |
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134 | register uint32_t tmp; |
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135 | __asm__ volatile ("mfpid %[tmp] \n\t" |
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136 | "stw %[tmp],0(%[tlb]) \n\t" |
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137 | "tlbre %[tmp],%[key],0 \n\t" |
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138 | "stw %[tmp],4(%[tlb]) \n\t" |
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139 | "tlbre %[tmp],%[key],1 \n\t" |
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140 | "stw %[tmp],8(%[tlb]) \n\t" |
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141 | "tlbre %[tmp],%[key],2 \n\t" |
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142 | "stw %[tmp],12(%[tlb]) \n\t" |
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143 | "sync \n\t" |
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144 | : [tmp]"=&r"(tmp) |
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145 | : [key]"r"(key), |
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146 | [tlb]"b"(tlb) |
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147 | ); |
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148 | } |
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149 | |
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150 | |
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151 | static void |
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152 | store(bsp_tlb_idx_t key, bsp_tlb_entry_t* tlb) |
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153 | { |
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154 | register uint32_t tmp; |
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155 | __asm__ volatile ("lwz %[tmp],0(%[tlb]) \n\t" |
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156 | "mtpid %[tmp] \n\t" |
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157 | "lwz %[tmp],4(%[tlb]) \n\t" |
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158 | "tlbwe %[tmp],%[idx],0 \n\t" |
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159 | "lwz %[tmp],8(%[tlb]) \n\t" |
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160 | "tlbwe %[tmp],%[idx],1 \n\t" |
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161 | "lwz %[tmp],12(%[tlb]) \n\t" |
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162 | "tlbwe %[tmp],%[idx],2 \n\t" |
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163 | : [tmp]"=&r"(tmp) |
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164 | : [tlb]"b"(tlb), |
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165 | [idx]"r"(key) |
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166 | ); |
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167 | } |
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168 | |
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169 | |
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170 | static void |
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171 | commit(void) |
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172 | { |
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173 | __asm__ volatile("isync \n\t"); |
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174 | } |
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175 | |
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176 | |
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177 | /* |
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178 | * Read a TLB entry from the hardware store the current settings in the |
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179 | * bsp_mmu_cache[] structure. |
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180 | * |
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181 | * The routine can perform this operation quietly or |
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182 | * print information to a file. |
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183 | * |
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184 | * 'idx': which TLB entry to access. |
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185 | * 'quiet': perform operation silently (no info printed) |
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186 | * if nonzero. |
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187 | * 'f': open FILE where to print information. May be |
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188 | * NULL in which case 'stdout' is used. |
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189 | * |
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190 | * RETURNS: |
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191 | * 0: success; TLB entry is VALID |
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192 | * +1: success but TLB entry is INVALID |
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193 | * < 0: error (-1: invalid argument) |
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194 | * (-2: driver not initialized) |
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195 | */ |
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196 | int |
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197 | bsp_mmu_update(bsp_tlb_idx_t key, bool quiet, FILE *f) |
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198 | { |
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199 | rtems_interrupt_level lvl; |
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200 | bsp_tlb_entry_t* tlb; |
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201 | int idx; |
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202 | |
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203 | idx = key; |
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204 | |
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205 | if ( idx < 0 || idx > NTLBS-1 ) |
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206 | return -1; |
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207 | |
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208 | if (!bsp_mmu_cache) |
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209 | return -2; |
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210 | |
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211 | tlb = bsp_mmu_cache + idx; |
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212 | |
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213 | rtems_interrupt_disable(lvl); |
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214 | |
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215 | fetch(idx, tlb); |
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216 | |
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217 | rtems_interrupt_enable(lvl); |
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218 | |
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219 | if ( tlb->w0.v ) { |
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220 | if ( !quiet ) { |
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221 | /* |
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222 | "TLB Entry # 0 spans EA range 0x00000000 - 0x00000000 |
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223 | "Mapping: VA [TS 0 / TID 0x00 / EPN 0x00000] -> RPN 0x00000" |
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224 | "Size: TSIZE 0x0 (4^sz KB = 000000 KB = 0x00000000 B) |
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225 | "Attributes: PERM 0x000 (ux/uw/ur/sx/sw/sr) WIMGE 0x00 U0-3 0x0" |
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226 | */ |
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227 | myprintf(f, |
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228 | "TLB Entry # %2d spans EA range 0x%08x - 0x%08x\n", |
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229 | idx, |
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230 | (tlb->w0.epn << 10), |
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231 | (tlb->w0.epn << 10) + (1024<<(2*tlb->w0.size)) - 1 |
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232 | ); |
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233 | |
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234 | myprintf(f, |
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235 | "Mapping: VA [TS %d / TID 0x%02x / EPN 0x%05x] -> RPN 0x%05"PRIx32"\n", |
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236 | tlb->w0.ts, tlb->id.tid, tlb->w0.epn, tlb->w1.rpn |
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237 | ); |
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238 | myprintf(f, |
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239 | "Size: TSIZE 0x%x (4^sz KB = %6d KB = 0x%08x B)\n", |
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240 | tlb->w0.size, (1<<(2*tlb->w0.size)), (1024<<(2*tlb->w0.size)) |
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241 | ); |
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242 | myprintf(f, |
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243 | "Properties: PERM 0x%03x (ux/uw/ur/sx/sw/sr) WIMGE 0x%02x U0-3 0x%01x\n", |
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244 | tlb->w2.perm, tlb->w2.wimge, tlb->w2.att |
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245 | ); |
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246 | } |
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247 | } else { |
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248 | if ( !quiet ) { |
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249 | myprintf(f, "TLB Entry # %2d <OFF> (size 0x%x = 0x%xb)\n", |
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250 | idx, tlb->w0.size, (1024<<(2*tlb->w0.size))); |
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251 | } |
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252 | return 1; |
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253 | } |
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254 | return 0; |
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255 | } |
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256 | |
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257 | /* Initialize cache. Should be done only once although this is not enforced. |
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258 | * |
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259 | * RETURNS: zero on success, nonzero on error; in this case the driver will |
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260 | * refuse to change TLB entries (other than disabling them). |
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261 | */ |
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262 | int |
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263 | bsp_mmu_initialize() |
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264 | { |
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265 | static bsp_tlb_entry_t mmu_cache[NTLBS]; |
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266 | bsp_tlb_entry_t* tlb = mmu_cache; /* Should malloc if it's not too early */ |
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267 | rtems_interrupt_level lvl; |
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268 | |
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269 | bsp_tlb_idx_t idx; |
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270 | rtems_interrupt_disable(lvl); |
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271 | for (idx=0; idx<NTLBS; tlb++, idx++) |
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272 | { |
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273 | fetch(idx, tlb); |
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274 | } |
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275 | rtems_interrupt_enable(lvl); |
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276 | |
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277 | bsp_mmu_cache = mmu_cache; |
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278 | return 0; |
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279 | } |
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280 | |
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281 | /* Find first free TLB entry by examining all entries' valid bit. The first |
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282 | * entry without the valid bit set is returned. |
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283 | * |
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284 | * RETURNS: A free TLB entry number. -1 if no entry can be found. |
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285 | */ |
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286 | bsp_tlb_idx_t |
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287 | bsp_mmu_find_first_free() |
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288 | { |
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289 | bsp_tlb_idx_t idx; |
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290 | bsp_tlb_entry_t entry; |
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291 | |
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292 | for (idx=0; idx<NTLBS; idx++) { |
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293 | register uint32_t tmp; |
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294 | __asm__ volatile ("tlbre %[tmp],%[idx],0 \n\t" |
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295 | "stw %[tmp],4(%[tlb]) \n\t" /* entry.w0 */ |
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296 | "sync \n\t" |
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297 | : [tmp]"=&r"(tmp) |
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298 | : [idx]"r"(idx), |
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299 | [tlb]"b"(&entry) |
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300 | : "memory" |
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301 | ); |
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302 | if (!(entry.w0.v)) |
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303 | break; |
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304 | } |
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305 | return (idx < NTLBS) ? idx : -1; |
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306 | } |
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307 | |
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308 | /* |
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309 | * Write TLB entry (can also be used to disable an entry). |
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310 | * |
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311 | * The routine checks against the cached data in |
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312 | * bsp_mmu_cache[] to prevent the user from generating |
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313 | * overlapping entries. |
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314 | * |
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315 | * 'idx': TLB entry # to manipulate |
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316 | * 'ea': Effective address (must be page aligned) |
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317 | * 'pa': Physical address (must be page aligned) |
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318 | * 'sz': Page size selector; page size is |
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319 | * 1024 * 2^(2*sz) bytes. |
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320 | * 'sz' may also be one of the following: |
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321 | * - page size in bytes ( >= 1024 ); the selector |
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322 | * value is then computed by this routine. |
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323 | * However, 'sz' must be a valid page size |
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324 | * or -1 will be returned. |
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325 | * - a value < 0 to invalidate/disable the |
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326 | * TLB entry. |
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327 | * 'flgs': Page's User-defined flags, permissions and WIMGE page attributes |
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328 | * 'tid': Translation ID |
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329 | * 'ts': Translation Space |
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330 | * 'erpn': Extended Real Page Number |
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331 | * |
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332 | * RETURNS: 0 on success, nonzero on error: |
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333 | * |
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334 | * >0: requested mapping would overlap with |
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335 | * existing mapping in other entry. Return |
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336 | * value gives conflicting entry + 1; i.e., |
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337 | * if a value of 4 is returned then the request |
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338 | * conflicts with existing mapping in entry 3. |
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339 | * -1: invalid argument |
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340 | * -3: driver not initialized (or initialization failed). |
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341 | * <0: other error |
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342 | */ |
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343 | bsp_tlb_idx_t |
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344 | bsp_mmu_write(bsp_tlb_idx_t idx, uint32_t ea, uint32_t pa, int sz, |
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345 | uint32_t flgs, uint32_t tid, uint32_t ts, uint32_t erpn) |
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346 | { |
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347 | bsp_tlb_entry_t tlb; |
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348 | uint32_t msk; |
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349 | bsp_tlb_idx_t lkup; |
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350 | rtems_interrupt_level lvl; |
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351 | |
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352 | if ( sz >= 1024 ) { |
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353 | /* Assume they literally specify a size */ |
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354 | msk = sz; |
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355 | sz = 0; |
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356 | while ( msk != (1024<<(sz+sz)) ) { |
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357 | if ( ++sz > 15 ) { |
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358 | return -1; |
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359 | } |
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360 | } |
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361 | /* OK, acceptable */ |
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362 | } |
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363 | |
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364 | msk = sz > 0 ? (1024<<(sz+sz)) - 1 : 0; |
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365 | |
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366 | if ( !bsp_mmu_cache && sz > 0 ) { |
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367 | myprintf(stderr,"MMU driver not initialized; refusing to enable any entry\n"); |
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368 | return -3; |
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369 | } |
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370 | |
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371 | if ( (ea & msk) || (pa & msk) ) { |
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372 | myprintf(stderr,"Misaligned EA (%08x) or PA (%08x) (mask is %08x)\n", ea, pa, msk); |
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373 | return -1; |
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374 | } |
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375 | |
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376 | if ( idx < 0 || idx > NTLBS-1 ) |
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377 | return -1; |
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378 | |
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379 | /* Not all 16 possible sizes are supported */ |
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380 | if ( sz == 6 || sz == 8 || sz > 9 ) { |
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381 | myprintf(stderr,"Invalid size %u = %08x = %u KB\n", sz, 1024<<(sz+sz), (1024<<(sz+sz))/1024); |
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382 | return -1; |
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383 | } |
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384 | |
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385 | if ( sz >=0 ) { |
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386 | lkup = bsp_mmu_match(ea, sz, tid, ts); |
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387 | |
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388 | if ( lkup < -1 ) { |
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389 | /* some error */ |
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390 | return lkup; |
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391 | } |
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392 | |
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393 | if ( lkup >= 0 && lkup != idx && (bsp_mmu_cache[lkup].w0.v != 0) ) { |
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394 | myprintf(stderr,"TLB #%i overlaps with requested mapping\n", lkup); |
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395 | bsp_mmu_update( lkup, false, stderr); |
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396 | return lkup+1; |
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397 | } |
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398 | } |
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399 | |
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400 | /* OK to proceed */ |
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401 | tlb.id.tid = tid; |
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402 | tlb.w0.v = sz >= 0; |
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403 | tlb.w0.ts = ts; |
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404 | tlb.w0.size = sz; |
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405 | tlb.w0.epn = (ea & (0xfffffc00 << (sz+sz))) >> 10; |
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406 | if (sz < 11) { |
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407 | tlb.w1.rpn = (pa & (0xfffffc00 << (sz+sz))) >> 10; |
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408 | tlb.w1.erpn = erpn; |
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409 | } |
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410 | else { |
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411 | sz -= 11; |
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412 | tlb.w1.rpn = 0; |
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413 | tlb.w1.erpn = (erpn & (0xf << (sz+sz))) & 0xf; |
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414 | } |
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415 | tlb.w2.att = (flgs & MMU_M_ATTR) >> MMU_V_ATTR; |
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416 | tlb.w2.wimge = (flgs & MMU_M_PROP) >> MMU_V_PROP; |
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417 | tlb.w2.perm = (flgs & MMU_M_PERM) >> MMU_V_PERM; |
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418 | |
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419 | rtems_interrupt_disable(lvl); |
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420 | |
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421 | store(idx, &tlb); |
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422 | |
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423 | commit(); |
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424 | |
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425 | rtems_interrupt_enable(lvl); |
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426 | |
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427 | /* update cache */ |
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428 | bsp_mmu_update(idx, true, 0); |
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429 | |
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430 | return 0; |
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431 | } |
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432 | |
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433 | /* |
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434 | * Check if a ea/tid/ts/sz mapping overlaps with an existing entry. |
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435 | * |
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436 | * 'ea': The Effective Address to match against |
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437 | * 'sz': The 'logarithmic' size selector; the page size |
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438 | * is 1024*2^(2*sz). |
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439 | * 'tid': Translation ID |
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440 | * 'ts': Translation Space |
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441 | * |
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442 | * RETURNS: |
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443 | * >= 0: index of the TLB entry that already provides a mapping |
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444 | * which overlaps within the ea range. |
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445 | * -1: SUCCESS (no conflicting entry found) |
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446 | * <=-2: ERROR (invalid input) |
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447 | */ |
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448 | bsp_tlb_idx_t |
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449 | bsp_mmu_match(uint32_t ea, int sz, uint32_t tid, uint32_t ts) |
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450 | { |
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451 | bsp_tlb_idx_t idx; |
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452 | uint32_t m,a; |
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453 | bsp_tlb_entry_t* tlb; |
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454 | |
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455 | if ( sz < 0 || sz == 6 || sz == 8 || sz > 9 ) |
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456 | return -4; |
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457 | |
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458 | sz = (1024<<(2*sz)); |
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459 | |
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460 | if ( !bsp_mmu_cache ) { |
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461 | /* cache not initialized */ |
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462 | return -3; |
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463 | } |
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464 | |
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465 | if ( ea & (sz-1) ) { |
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466 | /* misaligned ea */ |
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467 | return -2; |
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468 | } |
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469 | |
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470 | for ( idx=0, tlb=bsp_mmu_cache; idx<NTLBS; idx++, tlb++ ) { |
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471 | if ( ! tlb->w0.v ) |
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472 | continue; |
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473 | if ( tlb->id.tid && tlb->id.tid != tid ) |
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474 | continue; |
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475 | if ( tlb->w0.ts != ts ) |
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476 | continue; |
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477 | /* TID and TS match a valid entry */ |
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478 | m = (1024<<(2*tlb->w0.size)) - 1; |
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479 | /* calculate starting address of this entry */ |
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480 | a = tlb->w0.epn<<10; |
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481 | if ( ea <= a + m && ea + sz -1 >= a ) { |
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482 | /* overlap */ |
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483 | return idx; |
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484 | } |
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485 | } |
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486 | return -1; |
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487 | } |
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488 | |
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489 | /* Find TLB index that maps 'ea/tid/ts' combination |
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490 | * |
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491 | * 'ea': Effective address to match against |
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492 | * 'tid': Translation ID |
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493 | * 'ts': Translation Space |
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494 | * |
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495 | * RETURNS: index 'key' which indicates whether |
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496 | * the mapping was found. |
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497 | * |
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498 | * On error (no mapping) -1 is returned. |
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499 | */ |
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500 | bsp_tlb_idx_t |
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501 | bsp_mmu_find(uint32_t ea, uint32_t tid, uint32_t ts) |
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502 | { |
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503 | rtems_interrupt_level lvl; |
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504 | register uint32_t mmucr; |
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505 | register bsp_tlb_idx_t idx; |
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506 | register int failure; |
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507 | |
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508 | rtems_interrupt_disable(lvl); |
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509 | |
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510 | __asm__ volatile ("mfspr %[mmucr],0x3b2 \n\t" /* Save MMUCR */ |
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511 | : [mmucr]"=r"(mmucr) |
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512 | ); |
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513 | __asm__ volatile ("mtspr 0x3b2,%[tid] \n\t" |
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514 | "tlbsx. %[idx],0,%[ea] \n\t" /* Failure changes the index reg randomly. */ |
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515 | "mfcr %[failure] \n\t" |
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516 | "mtspr 0x3b2,%[mmucr] \n\t" /* Restore MMUCR */ |
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517 | : [idx]"=&r"(idx), |
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518 | [failure]"=&r"(failure) |
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519 | : [tid]"r"((mmucr & 0xfffeff00) | (ts << 16) | tid), |
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520 | [ea]"r"(ea), |
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521 | [mmucr]"r"(mmucr) |
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522 | : "cc" |
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523 | ); |
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524 | |
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525 | rtems_interrupt_enable(lvl); |
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526 | |
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527 | return (failure & 0x20000000) ? idx : -1; |
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528 | } |
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529 | |
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530 | /* Mark TLB entry as invalid ('disabled'). |
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531 | * |
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532 | * 'key': TLB entry (index). |
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533 | * |
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534 | * RETURNS: zero on success, nonzero on error (TLB unchanged). |
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535 | * |
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536 | * NOTE: If a TLB entry is disabled the associated |
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537 | * entry in bsp_mmu_cache[] is also |
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538 | * marked as disabled. |
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539 | */ |
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540 | int |
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541 | bsp_mmu_invalidate(bsp_tlb_idx_t key) |
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542 | { |
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543 | bsp_tlb_idx_t k0; |
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544 | rtems_interrupt_level lvl; |
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545 | bsp_tlb_entry_t tlb; |
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546 | |
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547 | /* minimal guard against bad key */ |
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548 | if ( key < 0 || key > NTLBS-1 ) |
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549 | return -1; |
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550 | |
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551 | /* Must not invalidate page 0 which holds vectors, text etc... */ |
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552 | k0 = bsp_mmu_find(0, 0, 0); |
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553 | if ( -1 == k0 ) { |
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554 | myprintf(stderr,"No mapping for address 0 found\n"); |
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555 | return -2; |
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556 | } |
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557 | |
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558 | /* NOTE: we assume PID is ignored */ |
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559 | if ( k0 == key ) { |
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560 | myprintf(stderr,"Cannot invalidate page holding address 0 (always needed)\n"); |
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561 | return -3; |
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562 | } |
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563 | |
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564 | rtems_interrupt_disable(lvl); |
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565 | |
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566 | fetch(key, &tlb); |
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567 | |
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568 | /* Invalidate old entries */ |
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569 | tlb.w0.v = 0; |
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570 | |
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571 | store(key, &tlb); |
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572 | |
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573 | commit(); |
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574 | |
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575 | /* Update cache */ |
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576 | bsp_mmu_cache[ key ].w0.v = tlb.w0.v; |
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577 | |
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578 | rtems_interrupt_enable(lvl); |
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579 | |
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580 | return 0; |
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581 | } |
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