[655bd39] | 1 | # Adapted from virtex BSP |
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| 2 | |
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| 3 | BSP NAME: virtex5 |
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| 4 | BOARD: N/A |
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| 5 | BUS: N/A |
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| 6 | CPU FAMILY: ppc |
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| 7 | CPU: PowerPC 440x5 |
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| 8 | COPROCESSORS: N/A |
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| 9 | MODE: 32 bit mode |
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| 10 | |
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| 11 | DEBUG MONITOR: |
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| 12 | |
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| 13 | PERIPHERALS |
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| 14 | =========== |
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| 15 | TIMERS: 440 internal |
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| 16 | SERIAL PORTS: none |
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| 17 | REAL-TIME CLOCK: none |
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| 18 | DMA: Xilinx virtex internal |
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| 19 | VIDEO: none |
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| 20 | SCSI: none |
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| 21 | NETWORKING: none |
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| 22 | |
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| 23 | DRIVER INFORMATION |
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| 24 | ================== |
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| 25 | CLOCK DRIVER: PPC Decrementer |
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| 26 | IOSUPP DRIVER: N/A |
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| 27 | SHMSUPP: N/A |
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| 28 | TIMER DRIVER: N/A |
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| 29 | TTY DRIVER: N/A |
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| 30 | |
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| 31 | STDIO |
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| 32 | ===== |
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| 33 | PORT: N/A |
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| 34 | ELECTRICAL: N/A |
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| 35 | BAUD: N/A |
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| 36 | BITS PER CHARACTER: N/A |
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| 37 | PARITY: N/A |
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| 38 | STOP BITS: N/A |
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| 39 | |
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| 40 | Notes |
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| 41 | ===== |
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| 42 | |
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| 43 | Board description |
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| 44 | ----------------- |
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| 45 | clock rate: 465 MHz |
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| 46 | ROM: N/A |
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| 47 | RAM: 4GByte DRAM |
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| 48 | |
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| 49 | Virtex only supports single processor operations. |
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| 50 | |
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| 51 | Porting |
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| 52 | ------- |
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| 53 | This board support package is written for a naked Virtex 5/PPC FPGA |
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| 54 | system. The rough features of such a board are described above. |
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| 55 | The BSP itself makes no assumptions on what is loaded in the FPGA, |
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| 56 | other than that the CPU has access to some memory, either on-board |
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| 57 | or external, from which code can be run. |
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| 58 | |
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| 59 | This BSP has been constructed so that an application of both firmware |
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| 60 | and software can be layered on top of it by supplying implementations |
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| 61 | for the various 'weak' symbols. These symbols are prefaced with the |
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| 62 | term 'app_'. Applications can thus be built outside of the RTEMS |
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| 63 | directory tree by linking with the appropriate libraries. |
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| 64 | |
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| 65 | The linkcmds file describes the memory layout. Included in this |
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| 66 | definition is a section of memory named MsgArea. Output sent to |
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| 67 | stdout is recorded in this area and can be dumped using the JTAG |
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| 68 | interface, for example. |
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| 69 | |
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| 70 | For adapting this BSP to other boards, the following files should be |
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| 71 | modified: |
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| 72 | |
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| 73 | - c/src/lib/libbsp/powerpc/virtex5/startup/linkcmds |
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| 74 | for the memory layout required |
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| 75 | |
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| 76 | - c/src/lib/libbsp/powerpc/virtex5/startup/bspstart.c |
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| 77 | Here you can select the clock source for the timers and the |
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| 78 | serial interface (system clock or external clock pin), the |
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| 79 | clock rates, etc. |
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| 80 | |
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| 81 | - c/src/lib/libbsp/powerpc/virtex5/include/bsp.h |
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| 82 | some BSP-related constants |
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| 83 | |
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| 84 | - c/src/lib/libbsp/powerpc/virtex5/* |
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| 85 | well, they should be generic, so there _should_ be no reason |
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| 86 | to mess around there (but who knows...) |
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