1 | /* |
---|
2 | * RTEMS virtex BSP |
---|
3 | * |
---|
4 | * This file contains the irq controller handler. |
---|
5 | * |
---|
6 | * Content moved from opbintctrl.c: |
---|
7 | * |
---|
8 | * This file contains definitions and declarations for the |
---|
9 | * Xilinx Off Processor Bus (OPB) Interrupt Controller |
---|
10 | */ |
---|
11 | |
---|
12 | /* |
---|
13 | * Author: Keith Robertson <kjrobert@alumni.uwaterloo.ca> |
---|
14 | * COPYRIGHT (c) 2005 Linn Products Ltd, Scotland. |
---|
15 | * Copyright (c) 2007 embedded brains GmbH. All rights reserved. |
---|
16 | * |
---|
17 | * The license and distribution terms for this file may be |
---|
18 | * found in the file LICENSE in this distribution or at |
---|
19 | * http://www.rtems.org/license/LICENSE. |
---|
20 | */ |
---|
21 | |
---|
22 | #include <bsp.h> |
---|
23 | #include <bsp/irq.h> |
---|
24 | #include <bsp/irq-generic.h> |
---|
25 | #include <bsp/vectors.h> |
---|
26 | |
---|
27 | #include <libcpu/powerpc-utility.h> |
---|
28 | |
---|
29 | /* |
---|
30 | * Acknowledge a mask of interrupts. |
---|
31 | */ |
---|
32 | static void set_iar(uint32_t mask) |
---|
33 | { |
---|
34 | *((volatile uint32_t *) (OPB_INTC_BASE + OPB_INTC_IAR)) = mask; |
---|
35 | } |
---|
36 | |
---|
37 | /* |
---|
38 | * Set IER state. Used to (dis)enable a mask of vectors. |
---|
39 | * If you only have to do one, use enable/disable_vector. |
---|
40 | */ |
---|
41 | static void set_ier(uint32_t mask) |
---|
42 | { |
---|
43 | *((volatile uint32_t *) (OPB_INTC_BASE + OPB_INTC_IER)) = mask; |
---|
44 | } |
---|
45 | |
---|
46 | /* |
---|
47 | * Retrieve contents of Interrupt Pending Register |
---|
48 | */ |
---|
49 | static uint32_t get_ipr(void) |
---|
50 | { |
---|
51 | uint32_t c = *((volatile uint32_t *) (OPB_INTC_BASE + OPB_INTC_IPR)); |
---|
52 | return c; |
---|
53 | } |
---|
54 | |
---|
55 | static void BSP_irq_enable_at_opbintc (rtems_irq_number irqnum) |
---|
56 | { |
---|
57 | *((volatile uint32_t *) (OPB_INTC_BASE + OPB_INTC_SIE)) |
---|
58 | = 1 << (irqnum - BSP_OPBINTC_IRQ_LOWEST_OFFSET); |
---|
59 | } |
---|
60 | |
---|
61 | static void BSP_irq_disable_at_opbintc (rtems_irq_number irqnum) |
---|
62 | { |
---|
63 | *((volatile uint32_t *) (OPB_INTC_BASE + OPB_INTC_CIE)) |
---|
64 | = 1 << (irqnum - BSP_OPBINTC_IRQ_LOWEST_OFFSET); |
---|
65 | } |
---|
66 | |
---|
67 | /* |
---|
68 | * IRQ Handler: this is called from the primary exception dispatcher |
---|
69 | */ |
---|
70 | static void BSP_irq_handle_at_opbintc(void) |
---|
71 | { |
---|
72 | uint32_t ipr; |
---|
73 | |
---|
74 | /* Get pending interrupts */ |
---|
75 | ipr = get_ipr(); |
---|
76 | |
---|
77 | if (ipr != 0) { |
---|
78 | /* Acknowledge all pending interrupts now and service them afterwards */ |
---|
79 | set_iar(ipr); |
---|
80 | |
---|
81 | do { |
---|
82 | /* Get highest priority pending interrupt */ |
---|
83 | uint32_t i = 31 - ppc_count_leading_zeros(ipr); |
---|
84 | |
---|
85 | ipr &= ~(1U << i); |
---|
86 | |
---|
87 | bsp_interrupt_handler_dispatch(i+BSP_OPBINTC_IRQ_LOWEST_OFFSET); |
---|
88 | } while (ipr != 0); |
---|
89 | } |
---|
90 | } |
---|
91 | |
---|
92 | /* |
---|
93 | * activate the interrupt controller |
---|
94 | */ |
---|
95 | static void opb_intc_init(void) |
---|
96 | { |
---|
97 | uint32_t i, mask = 0; |
---|
98 | |
---|
99 | /* mask off all interrupts */ |
---|
100 | set_ier(0x0); |
---|
101 | |
---|
102 | for (i = 0; i < OPB_INTC_IRQ_MAX; i++) { |
---|
103 | mask |= (1 << i); |
---|
104 | } |
---|
105 | |
---|
106 | /* make sure interupt status register is clear before we enable the interrupt controller */ |
---|
107 | *((volatile uint32_t *) (OPB_INTC_BASE + OPB_INTC_ISR)) = 0; |
---|
108 | |
---|
109 | /* acknowledge all interrupt sources */ |
---|
110 | set_iar(mask); |
---|
111 | |
---|
112 | /* Turn on normal hardware operation of interrupt controller */ |
---|
113 | *((volatile uint32_t *) (OPB_INTC_BASE + OPB_INTC_MER)) = |
---|
114 | (OPB_INTC_MER_HIE); |
---|
115 | |
---|
116 | /* Enable master interrupt switch for the interrupt controller */ |
---|
117 | *((volatile uint32_t *) (OPB_INTC_BASE + OPB_INTC_MER)) = |
---|
118 | (OPB_INTC_MER_HIE | OPB_INTC_MER_ME); |
---|
119 | } |
---|
120 | |
---|
121 | rtems_status_code bsp_interrupt_get_attributes( |
---|
122 | rtems_vector_number vector, |
---|
123 | rtems_interrupt_attributes *attributes |
---|
124 | ) |
---|
125 | { |
---|
126 | return RTEMS_SUCCESSFUL; |
---|
127 | } |
---|
128 | |
---|
129 | rtems_status_code bsp_interrupt_is_pending( |
---|
130 | rtems_vector_number vector, |
---|
131 | bool *pending |
---|
132 | ) |
---|
133 | { |
---|
134 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
---|
135 | bsp_interrupt_assert(pending != NULL); |
---|
136 | *pending = false; |
---|
137 | return RTEMS_UNSATISFIED; |
---|
138 | } |
---|
139 | |
---|
140 | rtems_status_code bsp_interrupt_raise(rtems_vector_number vector) |
---|
141 | { |
---|
142 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
---|
143 | return RTEMS_UNSATISFIED; |
---|
144 | } |
---|
145 | |
---|
146 | rtems_status_code bsp_interrupt_clear(rtems_vector_number vector) |
---|
147 | { |
---|
148 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
---|
149 | return RTEMS_UNSATISFIED; |
---|
150 | } |
---|
151 | |
---|
152 | rtems_status_code bsp_interrupt_vector_is_enabled( |
---|
153 | rtems_vector_number vector, |
---|
154 | bool *enabled |
---|
155 | ) |
---|
156 | { |
---|
157 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
---|
158 | bsp_interrupt_assert(enabled != NULL); |
---|
159 | *enabled = false; |
---|
160 | return RTEMS_UNSATISFIED; |
---|
161 | } |
---|
162 | |
---|
163 | rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector) |
---|
164 | { |
---|
165 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
---|
166 | |
---|
167 | if (BSP_IS_OPBINTC_IRQ(vector)) { |
---|
168 | BSP_irq_enable_at_opbintc(vector); |
---|
169 | } |
---|
170 | |
---|
171 | return RTEMS_SUCCESSFUL; |
---|
172 | } |
---|
173 | |
---|
174 | rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector) |
---|
175 | { |
---|
176 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
---|
177 | |
---|
178 | if (BSP_IS_OPBINTC_IRQ(vector)) { |
---|
179 | BSP_irq_disable_at_opbintc(vector); |
---|
180 | } |
---|
181 | |
---|
182 | return RTEMS_SUCCESSFUL; |
---|
183 | } |
---|
184 | |
---|
185 | static int C_dispatch_irq_handler(BSP_Exception_frame *frame, unsigned int excNum) |
---|
186 | { |
---|
187 | BSP_irq_handle_at_opbintc(); |
---|
188 | |
---|
189 | return 0; |
---|
190 | } |
---|
191 | |
---|
192 | void bsp_interrupt_facility_initialize(void) |
---|
193 | { |
---|
194 | rtems_status_code sc; |
---|
195 | |
---|
196 | opb_intc_init(); |
---|
197 | |
---|
198 | sc = ppc_exc_set_handler(ASM_EXT_VECTOR, C_dispatch_irq_handler); |
---|
199 | _Assert_Unused_variable_equals(sc, RTEMS_SUCCESSFUL); |
---|
200 | } |
---|