source: rtems/bsps/powerpc/virtex/irq/irq_init.c @ e560ee85

Last change on this file since e560ee85 was e560ee85, checked in by Joel Sherrill <joel@…>, on 03/01/22 at 21:38:55

bsps/powerpc/: Scripted embedded brains header file clean up

Updates #4625.

  • Property mode set to 100644
File size: 6.0 KB
Line 
1/*===============================================================*\
2| Project: RTEMS virtex BSP                                       |
3+-----------------------------------------------------------------+
4| Partially based on the code references which are named below.   |
5| Adaptions, modifications, enhancements and any recent parts of  |
6| the code are:                                                   |
7|                    Copyright (c) 2007                           |
8|                    embedded brains GmbH                         |
9|                    Obere Lagerstr. 30                           |
10|                    82178 Puchheim                             |
11|                    Germany                                      |
12|                    rtems@embedded-brains.de                     |
13+-----------------------------------------------------------------+
14| The license and distribution terms for this file may be         |
15| found in the file LICENSE in this distribution or at            |
16|                                                                 |
17| http://www.rtems.org/license/LICENSE.                           |
18|                                                                 |
19+-----------------------------------------------------------------+
20| this file contains the irq controller handler                   |
21\*===============================================================*/
22
23/*  Content moved from opbintctrl.c:
24 *
25 *  This file contains definitions and declarations for the
26 *  Xilinx Off Processor Bus (OPB) Interrupt Controller
27 *
28 *  Author: Keith Robertson <kjrobert@alumni.uwaterloo.ca>
29 *  COPYRIGHT (c) 2005 Linn Products Ltd, Scotland.
30 *
31 *  The license and distribution terms for this file may be
32 *  found in the file LICENSE in this distribution or at
33 *  http://www.rtems.org/license/LICENSE.
34 */
35
36#include <bsp.h>
37#include <bsp/irq.h>
38#include <bsp/irq-generic.h>
39#include <bsp/vectors.h>
40
41#include <libcpu/powerpc-utility.h>
42
43/*
44 * Acknowledge a mask of interrupts.
45 */
46static void set_iar(uint32_t mask)
47{
48  *((volatile uint32_t *) (OPB_INTC_BASE + OPB_INTC_IAR)) = mask;
49}
50
51/*
52 * Set IER state.  Used to (dis)enable a mask of vectors.
53 * If you only have to do one, use enable/disable_vector.
54 */
55static void set_ier(uint32_t mask)
56{
57  *((volatile uint32_t *) (OPB_INTC_BASE + OPB_INTC_IER)) = mask;
58}
59
60/*
61 * Retrieve contents of Interrupt Pending Register
62 */
63static uint32_t get_ipr(void)
64{
65  uint32_t c = *((volatile uint32_t *) (OPB_INTC_BASE + OPB_INTC_IPR));
66  return c;
67}
68
69static void BSP_irq_enable_at_opbintc (rtems_irq_number irqnum)
70{
71  *((volatile uint32_t *) (OPB_INTC_BASE + OPB_INTC_SIE))
72    = 1 << (irqnum - BSP_OPBINTC_IRQ_LOWEST_OFFSET);
73}
74
75static void BSP_irq_disable_at_opbintc (rtems_irq_number irqnum)
76{
77  *((volatile uint32_t *) (OPB_INTC_BASE + OPB_INTC_CIE))
78    = 1 << (irqnum - BSP_OPBINTC_IRQ_LOWEST_OFFSET);
79}
80
81/*
82 *  IRQ Handler: this is called from the primary exception dispatcher
83 */
84static void BSP_irq_handle_at_opbintc(void)
85{
86  uint32_t ipr;
87
88  /* Get pending interrupts */
89  ipr = get_ipr();
90
91  if (ipr != 0) {
92    /* Acknowledge all pending interrupts now and service them afterwards */
93    set_iar(ipr);
94
95    do {
96      /* Get highest priority pending interrupt */
97      uint32_t i = 31 - ppc_count_leading_zeros(ipr);
98
99      ipr &= ~(1U << i);
100
101      bsp_interrupt_handler_dispatch(i+BSP_OPBINTC_IRQ_LOWEST_OFFSET);
102    } while (ipr != 0);
103  }
104}
105
106/*
107 * activate the interrupt controller
108 */
109static void opb_intc_init(void)
110{
111  uint32_t i, mask = 0;
112
113  /* mask off all interrupts */
114  set_ier(0x0);
115
116  for (i = 0; i < OPB_INTC_IRQ_MAX; i++) {
117    mask |= (1 << i);
118  }
119
120  /* make sure interupt status register is clear before we enable the interrupt controller */
121  *((volatile uint32_t *) (OPB_INTC_BASE + OPB_INTC_ISR)) = 0;
122
123  /* acknowledge all interrupt sources */
124  set_iar(mask);
125
126  /* Turn on normal hardware operation of interrupt controller */
127  *((volatile uint32_t *) (OPB_INTC_BASE + OPB_INTC_MER)) =
128    (OPB_INTC_MER_HIE);
129
130  /* Enable master interrupt switch for the interrupt controller */
131  *((volatile uint32_t *) (OPB_INTC_BASE + OPB_INTC_MER)) =
132    (OPB_INTC_MER_HIE | OPB_INTC_MER_ME);
133}
134
135rtems_status_code bsp_interrupt_get_attributes(
136  rtems_vector_number         vector,
137  rtems_interrupt_attributes *attributes
138)
139{
140  return RTEMS_SUCCESSFUL;
141}
142
143rtems_status_code bsp_interrupt_is_pending(
144  rtems_vector_number vector,
145  bool               *pending
146)
147{
148  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
149  bsp_interrupt_assert(pending != NULL);
150  *pending = false;
151  return RTEMS_UNSATISFIED;
152}
153
154rtems_status_code bsp_interrupt_raise(rtems_vector_number vector)
155{
156  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
157  return RTEMS_UNSATISFIED;
158}
159
160rtems_status_code bsp_interrupt_clear(rtems_vector_number vector)
161{
162  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
163  return RTEMS_UNSATISFIED;
164}
165
166rtems_status_code bsp_interrupt_vector_is_enabled(
167  rtems_vector_number vector,
168  bool               *enabled
169)
170{
171  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
172  bsp_interrupt_assert(enabled != NULL);
173  *enabled = false;
174  return RTEMS_UNSATISFIED;
175}
176
177rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
178{
179  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
180
181  if (BSP_IS_OPBINTC_IRQ(vector)) {
182    BSP_irq_enable_at_opbintc(vector);
183  }
184
185  return RTEMS_SUCCESSFUL;
186}
187
188rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
189{
190  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
191
192  if (BSP_IS_OPBINTC_IRQ(vector)) {
193    BSP_irq_disable_at_opbintc(vector);
194  }
195
196  return RTEMS_SUCCESSFUL;
197}
198
199static int C_dispatch_irq_handler(BSP_Exception_frame *frame, unsigned int excNum)
200{
201  BSP_irq_handle_at_opbintc();
202
203  return 0;
204}
205
206void bsp_interrupt_facility_initialize(void)
207{
208  rtems_status_code sc;
209
210  opb_intc_init();
211
212  sc = ppc_exc_set_handler(ASM_EXT_VECTOR, C_dispatch_irq_handler);
213  _Assert_Unused_variable_equals(sc, RTEMS_SUCCESSFUL);
214}
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