source: rtems/bsps/powerpc/virtex/include/bsp/opbintctrl.h @ 2afb22b

5
Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.
  • Property mode set to 100644
File size: 1.8 KB
Line 
1/*  opbintctrl.h
2 *
3 *  This file contains definitions and declarations for the
4 *  Xilinx Off Processor Bus (OPB) Interrupt Controller
5 *
6 *  Author: Keith Robertson <kjrobert@alumni.uwaterloo.ca>
7 *  COPYRIGHT (c) 2005 by Linn Products Ltd, Scotland
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.rtems.org/license/LICENSE.
12 */
13
14#ifndef _INCLUDE_OPBINTCTRL_H
15#define _INCLUDE_OPBINTCTRL_H
16
17#include <rtems.h>
18#include <rtems/system.h>
19#include <rtems/score/isr.h>
20#include <rtems/irq.h>
21#include <bspopts.h>
22#include RTEMS_XPARAMETERS_H
23
24#define USE_GREG_INTERRUPTS
25
26#ifdef __cplusplus
27extern "C" {
28#endif
29
30
31/* extern XIntc InterruptController;
32 */
33
34
35/* Maximum number of IRQs.  Defined in vhdl model */
36#define OPB_INTC_IRQ_MAX          XPAR_INTC_MAX_NUM_INTR_INPUTS
37
38/* Width of INTC registers.  Defined in vhdl model */
39#define OPB_INTC_REGISTER_WIDTH   32
40
41/* Base Register address and register offsets.  Defined in vhdl model  */
42#define OPB_INTC_BASE             XPAR_INTC_SINGLE_BASEADDR
43
44
45
46
47
48/* Interrupt Status Register */
49#define OPB_INTC_ISR            0x0
50/* Interrupt Pending Register (ISR && IER) */
51#define OPB_INTC_IPR            0x4
52/* Interrupt Enable Register */
53#define OPB_INTC_IER            0x8
54/* Interrupt Acknowledge Register */
55#define OPB_INTC_IAR            0xC
56/* Set Interrupt Enable (same as read/mask/write to IER) */
57#define OPB_INTC_SIE            0x10
58/* Clear Interrupt Enable (same as read/mask/write to IER) */
59#define OPB_INTC_CIE            0x14
60/* Interrupt Vector Address (highest priority vector number from IPR) */
61#define OPB_INTC_IVR            0x18
62/* Master Enable Register */
63#define OPB_INTC_MER            0x1C
64
65/* Master Enable Register: Hardware Interrupt Enable */
66#define OPB_INTC_MER_HIE        0x2
67
68/* Master Enable Register: Master IRQ Enable */
69#define OPB_INTC_MER_ME         0x1
70
71#ifdef __cplusplus
72}
73#endif
74
75#endif /*  _INCLUDE_OPBINTCTRL_H */
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