source: rtems/bsps/powerpc/tqm8xx/start/mmutlbtab.c @ 9964895

5
Last change on this file since 9964895 was 9964895, checked in by Sebastian Huber <sebastian.huber@…>, on Apr 20, 2018 at 8:35:35 AM

bsps: Move startup files to bsps

Adjust build support files to new directory layout.

This patch is a part of the BSP source reorganization.

Update #3285.

  • Property mode set to 100644
File size: 4.5 KB
Line 
1/*===============================================================*\
2| Project: RTEMS TQM8xx BSP                                       |
3+-----------------------------------------------------------------+
4| This file has been adapted to MPC8xx by                         |
5|    Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>         |
6|                    Copyright (c) 2008                           |
7|                    Embedded Brains GmbH                         |
8|                    Obere Lagerstr. 30                           |
9|                    D-82178 Puchheim                             |
10|                    Germany                                      |
11|                    rtems@embedded-brains.de                     |
12|                                                                 |
13| See the other copyright notice below for the original parts.    |
14+-----------------------------------------------------------------+
15| The license and distribution terms for this file may be         |
16| found in the file LICENSE in this distribution or at            |
17|                                                                 |
18| http://www.rtems.org/license/LICENSE.                           |
19|                                                                 |
20+-----------------------------------------------------------------+
21| this file contains the console driver                           |
22\*===============================================================*/
23/* derived from: */
24/*
25 * mmutlbtab.c
26 *
27 * Copyright (c) 1999, National Research Council of Canada
28 *
29 * The license and distribution terms for this file may be
30 * found in the file LICENSE in this distribution or at
31 * http://www.rtems.org/license/LICENSE.
32 */
33
34#include <bsp.h>
35#include <mpc8xx/mmu.h>
36/*
37 * This MMU_TLB_table is used to statically initialize the Table Lookaside
38 * Buffers in the MMU of the TQM8xx board.
39 *
40 * We initialize the entries in both the instruction and data TLBs
41 * with the same values - a few bits relevant to the data TLB are unused
42 * in the instruction TLB.
43 *
44 * An Effective Page Number (EPN), Tablewalk Control Register (TWC) and
45 * Real Page Number (RPN) value are supplied in the table for each TLB entry.
46 *
47 * The instruction and data TLBs each can hold 32 entries, so _TLB_Table must
48 * not have more than 32 lines in it!
49 *
50 * We set up the virtual memory map so that virtual address of a
51 * location is equal to its real address.
52 */
53MMU_TLB_table_t MMU_TLB_table[] = {
54  /*
55   * DRAM: Start address 0x00000000, 128M,
56   *    ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy,
57   *    R/W,X for all, no ASID comparison, not cache-inhibited.
58   * EPN                TWC     RPN
59   */
60  { 0x00000200, 0x0D,   0x000009FD },   /* DRAM - PS=8M */
61  { 0x00800200, 0x0D,   0x008009FD },   /* DRAM - PS=8M */
62  { 0x01000200, 0x0D,   0x010009FD },   /* DRAM - PS=8M */
63  { 0x01800200, 0x0D,   0x018009FD },   /* DRAM - PS=8M */
64  { 0x02000200, 0x0D,   0x020009FD },   /* DRAM - PS=8M */
65  { 0x02800200, 0x0D,   0x028009FD },   /* DRAM - PS=8M */
66  { 0x03000200, 0x0D,   0x030009FD },   /* DRAM - PS=8M */
67  { 0x03800200, 0x0D,   0x038009FD },   /* DRAM - PS=8M */
68  { 0x04000200, 0x0D,   0x040009FD },   /* DRAM - PS=8M */
69  { 0x04800200, 0x0D,   0x048009FD },   /* DRAM - PS=8M */
70  { 0x05000200, 0x0D,   0x050009FD },   /* DRAM - PS=8M */
71  { 0x05800200, 0x0D,   0x058009FD },   /* DRAM - PS=8M */
72  { 0x06000200, 0x0D,   0x060009FD },   /* DRAM - PS=8M */
73  { 0x06800200, 0x0D,   0x068009FD },   /* DRAM - PS=8M */
74  { 0x07000200, 0x0D,   0x070009FD },   /* DRAM - PS=8M */
75  { 0x07800200, 0x0D,   0x078009FD },   /* DRAM - PS=8M */
76  /*
77   *
78   * (IMMR-SPRs) Dual Port RAM: Start address 0xFA200000, 16K,
79   *    ASID=0x0, APG=0x0, guarded memory, write-through data cache policy,
80   *    R/W,X for all, no ASID comparison, cache-inhibited.
81   *
82   *    Note: We use the value in MBXA/PG2, which is also the value that
83   *    EPPC-Bug programmed into our boards. The alternative is the value
84   *    in MBXA/PG1: 0xFFA00000. This value might well depend on the revision
85   *    of the firmware.
86   * EPN                TWC     RPN
87   */
88  { 0xFA200200, 0x13,   0xFA2009FF },   /* IMMR - PS=16K */
89  /*
90   *
91   * Flash: Start address 0x40000000, 8M,
92   *    ASID=0x0, APG=0x0, not guarded memory,
93   *    R/O,X for all, no ASID comparison, not cache-inhibited.
94   * EPN                TWC     RPN
95   */
96  { 0x40000200, 0x0D,   0x40000CFD }    /* Flash - PS=8M   */
97};
98
99/*
100 * MMU_N_TLB_Table_Entries is defined here because the size of the
101 * MMU_TLB_table is only known in this file.
102 */
103int MMU_N_TLB_Table_Entries = ( sizeof(MMU_TLB_table) / sizeof(MMU_TLB_table[0]) );
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