source: rtems/bsps/powerpc/tqm8xx/include/bsp/8xx_immap.h @ 7632906

5
Last change on this file since 7632906 was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

  • Property mode set to 100644
File size: 12.3 KB
Line 
1/*===============================================================*\
2| Project: RTEMS BSP support for TQ modules                       |
3+-----------------------------------------------------------------+
4| Partially based on the code references which are named below.   |
5| Adaptions, modifications, enhancements and any recent parts of  |
6| the code are:                                                   |
7|                    Copyright (c) 2007                           |
8|                    Embedded Brains GmbH                         |
9|                    Obere Lagerstr. 30                           |
10|                    D-82178 Puchheim                             |
11|                    Germany                                      |
12|                    rtems@embedded-brains.de                     |
13+-----------------------------------------------------------------+
14| The license and distribution terms for this file may be         |
15| found in the file LICENSE in this distribution or at            |
16|                                                                 |
17| http://www.rtems.org/license/LICENSE.                           |
18|                                                                 |
19+-----------------------------------------------------------------+
20| this file contains definitions to interact with TQC's           |
21|  processor modules                                              |
22\*===============================================================*/
23/* derived from mbx8xx BSP */
24/*
25 * MPC8xx Internal Memory Map
26 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
27 *
28 * The I/O on the MPC860 is comprised of blocks of special registers
29 * and the dual port ram for the Communication Processor Module.
30 * Within this space are functional units such as the SIU, memory
31 * controller, system timers, and other control functions.  It is
32 * a combination that I found difficult to separate into logical
33 * functional files.....but anyone else is welcome to try.  -- Dan
34 */
35#ifndef __IMMAP_8XX__
36#define __IMMAP_8XX__
37
38/* System configuration registers.
39*/
40typedef struct sys_conf {
41        unsigned int    sc_siumcr;
42        unsigned int    sc_sypcr;
43        unsigned int    sc_swt;
44        char            res1[2];
45        unsigned short  sc_swsr;
46        unsigned int    sc_sipend;
47        unsigned int    sc_simask;
48        unsigned int    sc_siel;
49        unsigned int    sc_sivec;
50        unsigned int    sc_tesr;
51        char            res2[0xc];
52        unsigned int    sc_sdcr;
53        char            res3[0x4c];
54} sysconf8xx_t;
55
56/* PCMCIA configuration registers.
57*/
58typedef struct pcmcia_conf {
59        unsigned int    pcmc_pbr0;
60        unsigned int    pcmc_por0;
61        unsigned int    pcmc_pbr1;
62        unsigned int    pcmc_por1;
63        unsigned int    pcmc_pbr2;
64        unsigned int    pcmc_por2;
65        unsigned int    pcmc_pbr3;
66        unsigned int    pcmc_por3;
67        unsigned int    pcmc_pbr4;
68        unsigned int    pcmc_por4;
69        unsigned int    pcmc_pbr5;
70        unsigned int    pcmc_por5;
71        unsigned int    pcmc_pbr6;
72        unsigned int    pcmc_por6;
73        unsigned int    pcmc_pbr7;
74        unsigned int    pcmc_por7;
75        char            res1[0x20];
76        unsigned int    pcmc_pgcra;
77        unsigned int    pcmc_pgcrb;
78        unsigned int    pcmc_pscr;
79        char            res2[4];
80        unsigned int    pcmc_pipr;
81        char            res3[4];
82        unsigned int    pcmc_per;
83        char            res4[4];
84} pcmconf8xx_t;
85
86/* Memory controller registers.
87*/
88typedef struct  mem_ctlr {
89        unsigned int    memc_br0;
90        unsigned int    memc_or0;
91        unsigned int    memc_br1;
92        unsigned int    memc_or1;
93        unsigned int    memc_br2;
94        unsigned int    memc_or2;
95        unsigned int    memc_br3;
96        unsigned int    memc_or3;
97        unsigned int    memc_br4;
98        unsigned int    memc_or4;
99        unsigned int    memc_br5;
100        unsigned int    memc_or5;
101        unsigned int    memc_br6;
102        unsigned int    memc_or6;
103        unsigned int    memc_br7;
104        unsigned int    memc_or7;
105        char            res1[0x24];
106        unsigned int    memc_mar;
107        unsigned int    memc_mcr;
108        char            res2[4];
109        unsigned int    memc_mamr;
110        unsigned int    memc_mbmr;
111        unsigned short  memc_mstat;
112        unsigned short  memc_mptpr;
113        unsigned int    memc_mdr;
114        char            res3[0x80];
115} memctl8xx_t;
116
117/* System Integration Timers.
118*/
119typedef struct  sys_int_timers {
120        unsigned short  sit_tbscr;
121        unsigned int    sit_tbreff0;
122        unsigned int    sit_tbreff1;
123        char            res1[0x14];
124        unsigned short  sit_rtcsc;
125        unsigned int    sit_rtc;
126        unsigned int    sit_rtsec;
127        unsigned int    sit_rtcal;
128        char            res2[0x10];
129        unsigned short  sit_piscr;
130        char            res3[2];
131        unsigned int    sit_pitc;
132        unsigned int    sit_pitr;
133        char            res4[0x34];
134} sit8xx_t;
135
136#define TBSCR_TBIRQ_MASK        ((unsigned short)0xff00)
137#define TBSCR_REFA              ((unsigned short)0x0080)
138#define TBSCR_REFB              ((unsigned short)0x0040)
139#define TBSCR_REFAE             ((unsigned short)0x0008)
140#define TBSCR_REFBE             ((unsigned short)0x0004)
141#define TBSCR_TBF               ((unsigned short)0x0002)
142#define TBSCR_TBE               ((unsigned short)0x0001)
143
144#define RTCSC_RTCIRQ_MASK       ((unsigned short)0xff00)
145#define RTCSC_SEC               ((unsigned short)0x0080)
146#define RTCSC_ALR               ((unsigned short)0x0040)
147#define RTCSC_38K               ((unsigned short)0x0010)
148#define RTCSC_SIE               ((unsigned short)0x0008)
149#define RTCSC_ALE               ((unsigned short)0x0004)
150#define RTCSC_RTF               ((unsigned short)0x0002)
151#define RTCSC_RTE               ((unsigned short)0x0001)
152
153#define PISCR_PIRQ_MASK         ((unsigned short)0xff00)
154#define PISCR_PS                ((unsigned short)0x0080)
155#define PISCR_PIE               ((unsigned short)0x0004)
156#define PISCR_PTF               ((unsigned short)0x0002)
157#define PISCR_PTE               ((unsigned short)0x0001)
158
159/* Clocks and Reset.
160*/
161typedef struct clk_and_reset {
162        unsigned int    car_sccr;
163        unsigned int    car_plprcr;
164        unsigned int    car_rsr;
165        char            res[0x74];        /* Reserved area                  */
166} car8xx_t;
167
168/* System Integration Timers keys.
169*/
170typedef struct sitk {
171        unsigned int    sitk_tbscrk;
172        unsigned int    sitk_tbreff0k;
173        unsigned int    sitk_tbreff1k;
174        unsigned int    sitk_tbk;
175        char            res1[0x10];
176        unsigned int    sitk_rtcsck;
177        unsigned int    sitk_rtck;
178        unsigned int    sitk_rtseck;
179        unsigned int    sitk_rtcalk;
180        char            res2[0x10];
181        unsigned int    sitk_piscrk;
182        unsigned int    sitk_pitck;
183        char            res3[0x38];
184} sitk8xx_t;
185
186/* Clocks and reset keys.
187*/
188typedef struct cark {
189        unsigned int    cark_sccrk;
190        unsigned int    cark_plprcrk;
191        unsigned int    cark_rsrk;
192        char            res[0x474];
193} cark8xx_t;
194
195/* The key to unlock registers maintained by keep-alive power.
196*/
197#define KAPWR_KEY       ((unsigned int)0x55ccaa33)
198
199/* LCD interface.  MPC821 Only.
200*/
201typedef struct lcd {
202        unsigned short  lcd_lcolr[16];
203        char            res[0x20];
204        unsigned int    lcd_lccr;
205        unsigned int    lcd_lchcr;
206        unsigned int    lcd_lcvcr;
207        char            res2[4];
208        unsigned int    lcd_lcfaa;
209        unsigned int    lcd_lcfba;
210        char            lcd_lcsr;
211        char            res3[0x7];
212} lcd8xx_t;
213
214/* I2C
215*/
216typedef struct i2c {
217        unsigned char   i2c_i2mod;
218        char            res1[3];
219        unsigned char   i2c_i2add;
220        char            res2[3];
221        unsigned char   i2c_i2brg;
222        char            res3[3];
223        unsigned char   i2c_i2com;
224        char            res4[3];
225        unsigned char   i2c_i2cer;
226        char            res5[3];
227        unsigned char   i2c_i2cmr;
228        char            res6[0x8b];
229} i2c8xx_t;
230
231/* DMA control/status registers.
232*/
233typedef struct sdma_csr {
234        char            res1[4];
235        unsigned int    sdma_sdar;
236        unsigned char   sdma_sdsr;
237        char            res3[3];
238        unsigned char   sdma_sdmr;
239        char            res4[3];
240        unsigned char   sdma_idsr1;
241        char            res5[3];
242        unsigned char   sdma_idmr1;
243        char            res6[3];
244        unsigned char   sdma_idsr2;
245        char            res7[3];
246        unsigned char   sdma_idmr2;
247        char            res8[0x13];
248} sdma8xx_t;
249
250/* Communication Processor Module Interrupt Controller.
251*/
252typedef struct cpm_ic {
253        unsigned short  cpic_civr;
254        char            res[0xe];
255        unsigned int    cpic_cicr;
256        unsigned int    cpic_cipr;
257        unsigned int    cpic_cimr;
258        unsigned int    cpic_cisr;
259} cpic8xx_t;
260
261/* Input/Output Port control/status registers.
262*/
263typedef struct io_port {
264        unsigned short  iop_padir;
265        unsigned short  iop_papar;
266        unsigned short  iop_paodr;
267        unsigned short  iop_padat;
268        char            res1[8];
269        unsigned short  iop_pcdir;
270        unsigned short  iop_pcpar;
271        unsigned short  iop_pcso;
272        unsigned short  iop_pcdat;
273        unsigned short  iop_pcint;
274        char            res2[6];
275        unsigned short  iop_pddir;
276        unsigned short  iop_pdpar;
277        char            res3[2];
278        unsigned short  iop_pddat;
279        char            res4[8];
280} iop8xx_t;
281
282/* Communication Processor Module Timers
283*/
284typedef struct cpm_timers {
285        unsigned short  cpmt_tgcr;
286        char            res1[0xe];
287        unsigned short  cpmt_tmr1;
288        unsigned short  cpmt_tmr2;
289        unsigned short  cpmt_trr1;
290        unsigned short  cpmt_trr2;
291        unsigned short  cpmt_tcr1;
292        unsigned short  cpmt_tcr2;
293        unsigned short  cpmt_tcn1;
294        unsigned short  cpmt_tcn2;
295        unsigned short  cpmt_tmr3;
296        unsigned short  cpmt_tmr4;
297        unsigned short  cpmt_trr3;
298        unsigned short  cpmt_trr4;
299        unsigned short  cpmt_tcr3;
300        unsigned short  cpmt_tcr4;
301        unsigned short  cpmt_tcn3;
302        unsigned short  cpmt_tcn4;
303        unsigned short  cpmt_ter1;
304        unsigned short  cpmt_ter2;
305        unsigned short  cpmt_ter3;
306        unsigned short  cpmt_ter4;
307        char            res2[8];
308} cpmtimer8xx_t;
309
310/* Finally, the Communication Processor stuff.....
311*/
312typedef struct scc {            /* Serial communication channels */
313        unsigned int    scc_gsmrl;
314        unsigned int    scc_gsmrh;
315        unsigned short  scc_pmsr;
316        char            res1[2];
317        unsigned short  scc_todr;
318        unsigned short  scc_dsr;
319        unsigned short  scc_scce;
320        char            res2[2];
321        unsigned short  scc_sccm;
322        char            res3;
323        unsigned char   scc_sccs;
324        char            res4[8];
325} scc_t;
326
327typedef struct smc {            /* Serial management channels */
328        char            res1[2];
329        unsigned short  smc_smcmr;
330        char            res2[2];
331        unsigned char   smc_smce;
332        char            res3[3];
333        unsigned char   smc_smcm;
334        char            res4[5];
335} smc_t;
336
337/* MPC860T Fast Ethernet Controller.  It isn't part of the CPM, but
338 * it fits within the address space.
339 */
340typedef struct fec {
341        unsigned int    fec_addr_low;           /* LS 32 bits of station address */
342        unsigned short  fec_addr_high;          /* MS 16 bits of address */
343        unsigned short  res1;
344        unsigned int    fec_hash_table_high;
345        unsigned int    fec_hash_table_low;
346        unsigned int    fec_r_des_start;
347        unsigned int    fec_x_des_start;
348        unsigned int    fec_r_buff_size;
349        unsigned int    res2[9];
350        unsigned int    fec_ecntrl;
351        unsigned int    fec_ievent;
352        unsigned int    fec_imask;
353        unsigned int    fec_ivec;
354        unsigned int    fec_r_des_active;
355        unsigned int    fec_x_des_active;
356        unsigned int    res3[10];
357        unsigned int    fec_mii_data;
358        unsigned int    fec_mii_speed;
359        unsigned int    res4[17];
360        unsigned int    fec_r_bound;
361        unsigned int    fec_r_fstart;
362        unsigned int    res5[6];
363        unsigned int    fec_x_fstart;
364        unsigned int    res6[17];
365        unsigned int    fec_fun_code;
366        unsigned int    res7[3];
367        unsigned int    fec_r_cntrl;
368        unsigned int    fec_r_hash;
369        unsigned int    res8[14];
370        unsigned int    fec_x_cntrl;
371        unsigned int    res9[0x1e];
372} fec_t;
373
374typedef struct comm_proc {
375        /* General control and status registers.
376        */
377        unsigned short  cp_cpcr;
378        char            res1[2];
379        unsigned short  cp_rccr;
380        char            res2[6];
381        unsigned short  cp_cpmcr1;
382        unsigned short  cp_cpmcr2;
383        unsigned short  cp_cpmcr3;
384        unsigned short  cp_cpmcr4;
385        char            res3[2];
386        unsigned short  cp_rter;
387        char            res4[2];
388        unsigned short  cp_rtmr;
389        char            res5[0x14];
390
391        /* Baud rate generators.
392        */
393        unsigned int    cp_brgc1;
394        unsigned int    cp_brgc2;
395        unsigned int    cp_brgc3;
396        unsigned int    cp_brgc4;
397
398        /* Serial Communication Channels.
399        */
400        scc_t   cp_scc[4];
401
402        /* Serial Management Channels.
403        */
404        smc_t   cp_smc[2];
405
406        /* Serial Peripheral Interface.
407        */
408        unsigned short  cp_spmode;
409        char            res6[4];
410        unsigned char   cp_spie;
411        char            res7[3];
412        unsigned char   cp_spim;
413        char            res8[2];
414        unsigned char   cp_spcom;
415        char            res9[2];
416
417        /* Parallel Interface Port.
418        */
419        char            res10[2];
420        unsigned short  cp_pipc;
421        char            res11[2];
422        unsigned short  cp_ptpr;
423        unsigned int    cp_pbdir;
424        unsigned int    cp_pbpar;
425        char            res12[2];
426        unsigned short  cp_pbodr;
427        unsigned int    cp_pbdat;
428        char            res13[0x18];
429
430        /* Serial Interface and Time Slot Assignment.
431        */
432        unsigned int    cp_simode;
433        unsigned char   cp_sigmr;
434        char            res14;
435        unsigned char   cp_sistr;
436        unsigned char   cp_sicmr;
437        char            res15[4];
438        unsigned int    cp_sicr;
439        unsigned int    cp_sirp;
440        char            res16[0x10c];
441        unsigned char   cp_siram[0x200];
442
443        /* The fast ethernet controller is not really part of the CPM,
444         * but it resides in the address space.
445         */
446        fec_t           cp_fec;
447        char            res18[0x1000];
448
449        /* Dual Ported RAM follows.
450         * There are many different formats for this memory area
451         * depending upon the devices used and options chosen.
452         */
453        unsigned char   cp_dpmem[0x1000];       /* BD / Data / ucode */
454        unsigned char   res19[0xc00];
455        unsigned char   cp_dparam[0x400];       /* Parameter RAM */
456} cpm8xx_t;
457
458/* Internal memory map.
459*/
460typedef struct immap {
461        sysconf8xx_t    im_siu_conf;    /* SIU Configuration */
462        pcmconf8xx_t    im_pcmcia;      /* PCMCIA Configuration */
463        memctl8xx_t     im_memctl;      /* Memory Controller */
464        sit8xx_t        im_sit;         /* System integration timers */
465        car8xx_t        im_clkrst;      /* Clocks and reset */
466        sitk8xx_t       im_sitk;        /* Sys int timer keys */
467        cark8xx_t       im_clkrstk;     /* Clocks and reset keys */
468        lcd8xx_t        im_lcd;         /* LCD (821 only) */
469        i2c8xx_t        im_i2c;         /* I2C control/status */
470        sdma8xx_t       im_sdma;        /* SDMA control/status */
471        cpic8xx_t       im_cpic;        /* CPM Interrupt Controller */
472        iop8xx_t        im_ioport;      /* IO Port control/status */
473        cpmtimer8xx_t   im_cpmtimer;    /* CPM timers */
474        cpm8xx_t        im_cpm;         /* Communication processor */
475} immap_t;
476
477#endif /* __IMMAP_8XX__ */
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