1 | /*===============================================================*\ |
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2 | | Project: RTEMS TQM8xx BSP | |
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3 | +-----------------------------------------------------------------+ |
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4 | | This file has been adapted to MPC8xx by | |
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5 | | Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> | |
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6 | | Copyright (c) 2008 | |
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7 | | Embedded Brains GmbH | |
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8 | | Obere Lagerstr. 30 | |
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9 | | D-82178 Puchheim | |
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10 | | Germany | |
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11 | | rtems@embedded-brains.de | |
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12 | | | |
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13 | | See the other copyright notice below for the original parts. | |
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14 | +-----------------------------------------------------------------+ |
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15 | | The license and distribution terms for this file may be | |
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16 | | found in the file LICENSE in this distribution or at | |
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17 | | | |
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18 | | http://www.rtems.org/license/LICENSE. | |
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19 | | | |
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20 | +-----------------------------------------------------------------+ |
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21 | | this file contains the console driver | |
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22 | \*===============================================================*/ |
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23 | /* derived from: */ |
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24 | /* |
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25 | * SMC1/2 SCC1..4 raw console serial I/O. |
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26 | * adapted to work with up to 4 SCC and 2 SMC |
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27 | * |
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28 | * This driver is an example of `TASK DRIVEN' `POLLING' or `INTERRUPT' I/O. |
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29 | * |
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30 | * To run with interrupt-driven I/O, ensure m8xx_smc1_interrupt |
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31 | * is set before calling the initialization routine. |
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32 | * |
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33 | * Author: |
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34 | * W. Eric Norum |
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35 | * Saskatchewan Accelerator Laboratory |
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36 | * University of Saskatchewan |
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37 | * Saskatoon, Saskatchewan, CANADA |
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38 | * eric@skatter.usask.ca |
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39 | * |
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40 | * COPYRIGHT (c) 1989-1998. |
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41 | * On-Line Applications Research Corporation (OAR). |
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42 | * Copyright assigned to U.S. Government, 1994. |
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43 | * |
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44 | * The license and distribution terms for this file may be |
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45 | * found in the file LICENSE in this distribution or at |
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46 | * http://www.OARcorp.com/rtems/license.html. |
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47 | */ |
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48 | |
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49 | #include <unistd.h> |
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50 | |
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51 | #include <rtems.h> |
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52 | #include <rtems/console.h> |
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53 | #include <rtems/termiostypes.h> |
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54 | #include <rtems/bspIo.h> |
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55 | #include <rtems/error.h> |
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56 | |
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57 | #include <bsp.h> |
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58 | #include <mpc8xx.h> |
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59 | #include <bsp/irq.h> |
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60 | |
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61 | /* |
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62 | * Interrupt-driven input buffer |
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63 | */ |
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64 | #define RXBUFSIZE 16 |
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65 | |
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66 | #define M8xx_SICR_BRG1 (0) |
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67 | #define M8xx_SICR_BRG2 (1) |
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68 | #define M8xx_SICR_BRG3 (2) |
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69 | #define M8xx_SICR_BRG4 (3) |
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70 | |
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71 | #define M8xx_SICR_SCCRX_MSK(scc) (( 7) << (((scc))*8+3)) |
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72 | #define M8xx_SICR_SCCRX(scc,clk) ((clk) << (((scc))*8+3)) |
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73 | |
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74 | #define M8xx_SICR_SCCTX_MSK(scc) (( 7) << (((scc))*8+0)) |
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75 | #define M8xx_SICR_SCCTX(scc,clk) ((clk) << (((scc))*8+0)) |
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76 | |
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77 | #define M8xx_SIMODE_SMCCS(smc,clk) ((clk) << ((smc)*16+12)) |
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78 | #define M8xx_SIMODE_SMCCS_MSK(smc) M8xx_SIMODE_SMCCS(smc,7) |
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79 | |
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80 | #define CONS_CHN_CNT 6 |
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81 | #define CONS_CHN_SCC1 0 |
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82 | #define CONS_CHN_SCC2 1 |
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83 | #define CONS_CHN_SCC3 2 |
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84 | #define CONS_CHN_SCC4 3 |
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85 | #define CONS_CHN_SMC1 4 |
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86 | #define CONS_CHN_SMC2 5 |
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87 | #define CONS_CHN_NONE -1 |
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88 | |
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89 | /* |
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90 | * possible identifiers for bspopts.h: CONS_SxCy_MODE |
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91 | */ |
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92 | #define CONS_MODE_UNUSED -1 |
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93 | #define CONS_MODE_POLLED TERMIOS_POLLED |
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94 | #define CONS_MODE_IRQ TERMIOS_IRQ_DRIVEN |
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95 | |
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96 | #define CHN_IS_SCC(chan) ((chan) < CONS_CHN_SMC1) |
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97 | |
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98 | #define BRG_CNT 4 |
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99 | |
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100 | #define MAX_IDL_DEFAULT 10 |
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101 | #define DEVICEPREFIX "tty" |
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102 | |
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103 | /* |
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104 | * I/O buffers and pointers to buffer descriptors |
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105 | */ |
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106 | #define SCC_RXBD_CNT 4 |
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107 | #define SCC_TXBD_CNT 4 |
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108 | typedef volatile char sccRxBuf_t[SCC_RXBD_CNT][RXBUFSIZE]; |
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109 | |
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110 | /* |
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111 | * Interrupt-driven callback |
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112 | */ |
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113 | typedef struct m8xx_console_chan_desc_s { |
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114 | rtems_termios_device_context base; |
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115 | volatile m8xxBufferDescriptor_t *sccFrstRxBd; |
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116 | volatile m8xxBufferDescriptor_t *sccCurrRxBd; |
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117 | volatile m8xxBufferDescriptor_t *sccFrstTxBd; |
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118 | volatile m8xxBufferDescriptor_t *sccPrepTxBd; |
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119 | volatile m8xxBufferDescriptor_t *sccDequTxBd; |
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120 | bool is_scc; /* true for SCC */ |
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121 | struct { |
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122 | volatile m8xxSCCparms_t *sccp; |
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123 | volatile m8xxSMCparms_t *smcp; |
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124 | } parms; |
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125 | struct { |
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126 | volatile m8xxSCCRegisters_t *sccr; |
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127 | volatile m8xxSMCRegisters_t *smcr; |
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128 | } regs; |
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129 | int chan; |
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130 | rtems_termios_device_mode mode; |
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131 | rtems_vector_number ivec_src; |
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132 | int cr_chan_code; |
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133 | int brg_used; |
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134 | sccRxBuf_t *rxBuf; |
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135 | } m8xx_console_chan_desc_t; |
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136 | |
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137 | m8xx_console_chan_desc_t m8xx_console_chan_desc[CONS_CHN_CNT] = { |
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138 | /* SCC1 */ |
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139 | { .is_scc = true, |
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140 | .parms = {(m8xxSCCparms_t *)&(m8xx.scc1p),NULL}, |
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141 | .regs = {&(m8xx.scc1),NULL}, |
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142 | .chan = CONS_CHN_SCC1, |
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143 | .ivec_src = BSP_CPM_IRQ_SCC1, |
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144 | .cr_chan_code = M8xx_CR_CHAN_SCC1, |
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145 | .brg_used = -1}, |
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146 | /* SCC2 */ |
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147 | { .is_scc = true, |
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148 | .parms = {&(m8xx.scc2p),NULL}, |
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149 | .regs = {&(m8xx.scc2),NULL}, |
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150 | .chan = CONS_CHN_SCC2, |
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151 | .ivec_src = BSP_CPM_IRQ_SCC2, |
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152 | .cr_chan_code = M8xx_CR_CHAN_SCC2, |
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153 | .brg_used = -1}, |
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154 | /* SCC3 */ |
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155 | { .is_scc = true, |
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156 | .parms = {&(m8xx.scc3p),NULL}, |
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157 | .regs = {&(m8xx.scc3),NULL}, |
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158 | .chan = CONS_CHN_SCC3, |
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159 | .ivec_src = BSP_CPM_IRQ_SCC3, |
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160 | .cr_chan_code = M8xx_CR_CHAN_SCC3, |
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161 | .brg_used = -1}, |
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162 | /* SCC4 */ |
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163 | { .is_scc = true, |
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164 | .parms = {&(m8xx.scc4p),NULL}, |
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165 | .regs = {&(m8xx.scc4),NULL}, |
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166 | .chan = CONS_CHN_SCC4, |
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167 | .ivec_src = BSP_CPM_IRQ_SCC4, |
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168 | .cr_chan_code = M8xx_CR_CHAN_SCC4, |
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169 | .brg_used = -1}, |
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170 | /* SMC1 */ |
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171 | { .is_scc = false, |
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172 | .parms = {NULL,&(m8xx.smc1p)}, |
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173 | .regs = {NULL,&(m8xx.smc1)}, |
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174 | .chan = CONS_CHN_SMC1, |
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175 | .ivec_src = BSP_CPM_IRQ_SMC1, |
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176 | .cr_chan_code = M8xx_CR_CHAN_SMC1, |
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177 | .brg_used = -1}, |
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178 | /* SMC2 */ |
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179 | { .is_scc = false, |
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180 | .parms = {NULL,&(m8xx.smc2p)}, |
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181 | .regs = {NULL,&(m8xx.smc2)}, |
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182 | .chan = CONS_CHN_SMC2, |
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183 | .ivec_src = BSP_CPM_IRQ_SMC2_OR_PIP, |
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184 | .cr_chan_code = M8xx_CR_CHAN_SMC2, |
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185 | .brg_used = -1}}; |
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186 | |
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187 | #define CHN_PARAM_GET(cd,param) \ |
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188 | (cd->is_scc \ |
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189 | ? cd->parms.sccp->param \ |
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190 | : cd->parms.smcp->param) |
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191 | |
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192 | #define CHN_PARAM_SET(cd,param,value) \ |
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193 | do {if (cd->is_scc) \ |
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194 | cd->parms.sccp->param = value; \ |
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195 | else \ |
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196 | cd->parms.smcp->param = value; \ |
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197 | } while (0) |
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198 | |
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199 | #define CHN_EVENT_GET(cd) \ |
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200 | (cd->is_scc \ |
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201 | ? cd->regs.sccr->scce \ |
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202 | : cd->regs.smcr->smce) |
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203 | |
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204 | #define CHN_EVENT_CLR(cd,mask) \ |
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205 | do { \ |
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206 | if (cd->is_scc) \ |
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207 | cd->regs.sccr->scce = (mask); \ |
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208 | else \ |
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209 | cd->regs.smcr->smce = (mask); \ |
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210 | }while (0) |
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211 | |
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212 | #define CHN_MASK_GET(cd) \ |
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213 | (cd->is_scc \ |
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214 | ? cd->regs.sccr->sccm \ |
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215 | : cd->regs.smcr->smcm) |
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216 | |
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217 | #define CHN_MASK_SET(cd,mask) \ |
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218 | do { \ |
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219 | if (cd->is_scc) \ |
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220 | cd->regs.sccr->sccm = (mask); \ |
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221 | else \ |
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222 | cd->regs.smcr->smcm = (mask); \ |
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223 | }while (0) |
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224 | |
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225 | /* |
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226 | * Compute baud-rate-generator configuration register value |
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227 | */ |
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228 | static uint32_t |
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229 | sccBRGval (int baud) |
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230 | { |
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231 | int divisor; |
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232 | int div16 = 0; |
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233 | |
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234 | divisor = ((BSP_bus_frequency / 16) + (baud / 2)) / baud; |
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235 | if (divisor > 4096) { |
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236 | div16 = 1; |
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237 | divisor = (divisor + 8) / 16; |
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238 | } |
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239 | return M8xx_BRG_EN | M8xx_BRG_EXTC_BRGCLK | ((divisor - 1) << 1) | div16; |
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240 | } |
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241 | |
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242 | typedef struct { |
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243 | uint32_t reg_content; |
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244 | int link_cnt; |
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245 | }brg_state_t; |
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246 | brg_state_t scc_brg_state[BRG_CNT]; |
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247 | |
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248 | /* |
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249 | * initialize brg_state |
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250 | */ |
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251 | static void sccBRGinit(void) |
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252 | { |
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253 | int brg_idx; |
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254 | |
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255 | for (brg_idx = 0;brg_idx < BRG_CNT;brg_idx++) { |
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256 | scc_brg_state[brg_idx].reg_content = 0; |
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257 | scc_brg_state[brg_idx].link_cnt = 0; |
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258 | } |
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259 | #ifndef MDE360 |
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260 | /* |
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261 | * on ZEM40, init CLK4/5 inputs |
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262 | */ |
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263 | m8xx.papar |= ((1 << 11) | (1 << 12)); |
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264 | m8xx.padir &= ~((1 << 11) | (1 << 12)); |
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265 | #endif |
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266 | } |
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267 | |
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268 | #if CONS_USE_EXT_CLK |
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269 | /* |
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270 | * input clock frq for CPM clock inputs |
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271 | */ |
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272 | static uint32_t clkin_frq[2][4] = { |
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273 | #ifdef MDE360 |
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274 | {0,0,0,0}, |
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275 | {0,0,0,0} |
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276 | #else |
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277 | {0,0,0,1843000}, |
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278 | {1843000,0,0,0} |
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279 | #endif |
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280 | }; |
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281 | #endif |
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282 | |
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283 | /* |
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284 | * allocate, set and connect baud rate generators |
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285 | * FIXME: or clock input |
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286 | * FIXME: set pin to be clock input |
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287 | */ |
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288 | |
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289 | static bool sccBRGalloc(m8xx_console_chan_desc_t *cd,int baud) |
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290 | { |
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291 | rtems_interrupt_level level; |
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292 | uint32_t reg_val; |
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293 | int old_brg; |
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294 | int new_brg = -1; |
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295 | int brg_idx; |
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296 | #if CONS_USE_EXT_CLK |
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297 | int clk_group; |
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298 | int clk_sel; |
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299 | #endif |
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300 | |
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301 | old_brg = cd->brg_used; |
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302 | /* compute brg register contents needed */ |
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303 | reg_val = sccBRGval(baud); |
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304 | |
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305 | #if CONS_EXT_CLK |
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306 | /* search for clock input with this frq */ |
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307 | clk_group = ((chan == CONS_CHN_SCC3) || |
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308 | (chan == CONS_CHN_SCC4) || |
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309 | (chan == CONS_CHN_SMC2)) ? 1 : 0; |
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310 | |
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311 | for (clk_sel = 0, new_brg = -1; |
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312 | (clk_sel < 4) && (new_brg < 0); |
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313 | clk_sel++) { |
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314 | if (baud == (clkin_frq[clk_group][clk_sel] / 16)) { |
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315 | new_brg = clk_sel + 4; |
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316 | } |
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317 | } |
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318 | #endif |
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319 | |
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320 | rtems_interrupt_disable(level); |
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321 | |
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322 | if (new_brg < 0) { |
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323 | /* search for brg with this settings */ |
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324 | for (brg_idx = 0; |
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325 | (new_brg < 0) && (brg_idx < BRG_CNT); |
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326 | brg_idx++) { |
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327 | if (scc_brg_state[brg_idx].reg_content == reg_val) { |
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328 | new_brg = brg_idx; |
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329 | } |
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330 | } |
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331 | /* |
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332 | * if not found: check, whether brg currently in use |
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333 | * is linked only from our channel |
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334 | */ |
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335 | if ((new_brg < 0) && |
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336 | (old_brg >= 0) && |
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337 | (scc_brg_state[old_brg].link_cnt == 1)) { |
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338 | new_brg = old_brg; |
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339 | } |
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340 | /* if not found: search for unused brg, set it */ |
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341 | for (brg_idx = 0; |
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342 | (new_brg < 0) && (brg_idx < BRG_CNT); |
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343 | brg_idx++) { |
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344 | if (scc_brg_state[brg_idx].link_cnt == 0) { |
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345 | new_brg = brg_idx; |
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346 | } |
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347 | } |
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348 | } |
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349 | |
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350 | /* decrease old link count */ |
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351 | if ((old_brg >= 0) && |
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352 | (old_brg < 4)) { |
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353 | scc_brg_state[old_brg].link_cnt--; |
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354 | } |
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355 | /* increase new brg link count, set brg */ |
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356 | if ((new_brg >= 0) && |
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357 | (new_brg < 4)) { |
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358 | scc_brg_state[new_brg].link_cnt++; |
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359 | scc_brg_state[new_brg].reg_content = reg_val; |
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360 | (&m8xx.brgc1)[new_brg] = reg_val; |
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361 | } |
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362 | rtems_interrupt_enable(level); |
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363 | |
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364 | /* connect to scc/smc */ |
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365 | if (new_brg >= 0) { |
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366 | cd->brg_used = new_brg; |
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367 | /* |
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368 | * Put SCC in NMSI mode, connect SCC to BRG or CLKx |
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369 | */ |
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370 | if (cd->is_scc) { |
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371 | m8xx.sicr = ((m8xx.sicr & ~(M8xx_SICR_SCCRX_MSK(cd->chan) | |
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372 | M8xx_SICR_SCCTX_MSK(cd->chan))) | |
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373 | M8xx_SICR_SCCRX(cd->chan,new_brg)| |
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374 | M8xx_SICR_SCCTX(cd->chan,new_brg)); |
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375 | } |
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376 | else { |
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377 | /* connect SMC to BRGx or CLKx... */ |
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378 | m8xx.simode = ((m8xx.simode & ~(M8xx_SIMODE_SMCCS_MSK(cd->chan - CONS_CHN_SMC1)))| |
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379 | M8xx_SIMODE_SMCCS(cd->chan - CONS_CHN_SMC1,new_brg)); |
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380 | } |
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381 | |
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382 | return true; |
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383 | } else { |
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384 | return false; |
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385 | } |
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386 | } |
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387 | |
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388 | |
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389 | /* |
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390 | * Hardware-dependent portion of tcsetattr(). |
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391 | */ |
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392 | static bool |
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393 | sccSetAttributes (rtems_termios_device_context *base, const struct termios *t) |
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394 | { |
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395 | m8xx_console_chan_desc_t *cd = (m8xx_console_chan_desc_t *)base; |
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396 | speed_t speed; |
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397 | rtems_termios_baud_t baud; |
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398 | |
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399 | speed = cfgetispeed(t); |
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400 | if (speed == B0) { |
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401 | speed = cfgetospeed(t); |
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402 | } |
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403 | |
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404 | baud = rtems_termios_baud_to_number(speed); |
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405 | if (baud == 0) { |
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406 | return false; |
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407 | } |
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408 | |
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409 | return sccBRGalloc(cd,baud); |
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410 | } |
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411 | |
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412 | /* |
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413 | * Interrupt handler |
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414 | */ |
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415 | static rtems_isr |
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416 | sccInterruptHandler (void *arg) |
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417 | { |
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418 | rtems_termios_tty *tty = arg; |
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419 | m8xx_console_chan_desc_t *cd = rtems_termios_get_device_context(tty); |
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420 | |
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421 | /* |
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422 | * Buffer received? |
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423 | */ |
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424 | if (CHN_EVENT_GET(cd) & 0x1) { |
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425 | /* |
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426 | * clear SCC event flag |
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427 | */ |
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428 | CHN_EVENT_CLR(cd,0x01); |
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429 | /* |
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430 | * process event |
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431 | */ |
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432 | while ((cd->sccCurrRxBd->status & M8xx_BD_EMPTY) == 0) { |
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433 | rtems_cache_invalidate_multiple_data_lines((void *)cd->sccCurrRxBd->buffer, |
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434 | cd->sccCurrRxBd->length); |
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435 | rtems_termios_enqueue_raw_characters (tty, |
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436 | (char *)cd->sccCurrRxBd->buffer, |
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437 | cd->sccCurrRxBd->length); |
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438 | /* |
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439 | * clear status |
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440 | */ |
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441 | cd->sccCurrRxBd->status = |
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442 | (cd->sccCurrRxBd->status |
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443 | & (M8xx_BD_WRAP | M8xx_BD_INTERRUPT)) |
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444 | | M8xx_BD_EMPTY; |
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445 | /* |
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446 | * advance to next BD |
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447 | */ |
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448 | if ((cd->sccCurrRxBd->status & M8xx_BD_WRAP) != 0) { |
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449 | cd->sccCurrRxBd = cd->sccFrstRxBd; |
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450 | } |
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451 | else { |
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452 | cd->sccCurrRxBd++; |
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453 | } |
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454 | } |
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455 | } |
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456 | /* |
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457 | * Buffer transmitted? |
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458 | */ |
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459 | if (CHN_EVENT_GET(cd) & 0x2) { |
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460 | /* |
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461 | * then clear interrupt event bit |
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462 | */ |
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463 | CHN_EVENT_CLR(cd,0x2); |
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464 | /* |
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465 | * and signal successful transmit to termios |
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466 | */ |
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467 | /* |
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468 | * FIXME: multiple dequeue calls for multiple buffers |
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469 | */ |
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470 | while((cd->sccDequTxBd != cd->sccPrepTxBd) && |
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471 | ((cd->sccDequTxBd->status & M8xx_BD_READY) == 0)) { |
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472 | rtems_termios_dequeue_characters (tty, cd->sccDequTxBd->length); |
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473 | /* |
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474 | * advance to next BD |
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475 | */ |
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476 | if ((cd->sccDequTxBd->status & M8xx_BD_WRAP) != 0) { |
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477 | cd->sccDequTxBd = cd->sccFrstTxBd; |
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478 | } |
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479 | else { |
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480 | cd->sccDequTxBd++; |
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481 | } |
---|
482 | } |
---|
483 | } |
---|
484 | } |
---|
485 | |
---|
486 | static void |
---|
487 | mpc8xx_console_irq_on(m8xx_console_chan_desc_t *cd) |
---|
488 | { |
---|
489 | CHN_MASK_SET(cd, 3); /* Enable TX and RX interrupts */ |
---|
490 | } |
---|
491 | |
---|
492 | static void |
---|
493 | sccInitialize (m8xx_console_chan_desc_t *cd) |
---|
494 | { |
---|
495 | int i; |
---|
496 | /* |
---|
497 | * allocate buffers |
---|
498 | * FIXME: use a cache-line size boundary alloc here |
---|
499 | */ |
---|
500 | cd->rxBuf = rtems_cache_aligned_malloc(sizeof(*cd->rxBuf)); |
---|
501 | if (cd->rxBuf == NULL) { |
---|
502 | rtems_panic("Cannot allocate console rx buffer\n"); |
---|
503 | } |
---|
504 | |
---|
505 | /* |
---|
506 | * Allocate buffer descriptors |
---|
507 | */ |
---|
508 | cd->sccCurrRxBd = |
---|
509 | cd->sccFrstRxBd = m8xx_bd_allocate(SCC_RXBD_CNT); |
---|
510 | cd->sccPrepTxBd = |
---|
511 | cd->sccDequTxBd = |
---|
512 | cd->sccFrstTxBd = m8xx_bd_allocate(SCC_TXBD_CNT); |
---|
513 | switch(cd->chan) { |
---|
514 | case CONS_CHN_SCC1: |
---|
515 | /* |
---|
516 | * Configure port A pins to enable TXD1 and RXD1 pins |
---|
517 | * FIXME: add setup for modem control lines.... |
---|
518 | */ |
---|
519 | m8xx.papar |= 0x03; |
---|
520 | m8xx.padir &= ~0x03; |
---|
521 | |
---|
522 | /* |
---|
523 | * Configure port C pins to enable RTS1 pins (static active low) |
---|
524 | */ |
---|
525 | m8xx.pcpar &= ~0x01; |
---|
526 | m8xx.pcso &= ~0x01; |
---|
527 | m8xx.pcdir |= 0x01; |
---|
528 | m8xx.pcdat &= ~0x01; |
---|
529 | break; |
---|
530 | case CONS_CHN_SCC2: |
---|
531 | /* |
---|
532 | * Configure port A pins to enable TXD2 and RXD2 pins |
---|
533 | * FIXME: add setup for modem control lines.... |
---|
534 | */ |
---|
535 | m8xx.papar |= 0x0C; |
---|
536 | m8xx.padir &= ~0x0C; |
---|
537 | |
---|
538 | /* |
---|
539 | * Configure port C pins to enable RTS2 pins (static active low) |
---|
540 | */ |
---|
541 | m8xx.pcpar &= ~0x02; |
---|
542 | m8xx.pcso &= ~0x02; |
---|
543 | m8xx.pcdir |= 0x02; |
---|
544 | m8xx.pcdat &= ~0x02; |
---|
545 | break; |
---|
546 | case CONS_CHN_SCC3: |
---|
547 | /* |
---|
548 | * Configure port A pins to enable TXD3 and RXD3 pins |
---|
549 | * FIXME: add setup for modem control lines.... |
---|
550 | */ |
---|
551 | m8xx.papar |= 0x30; |
---|
552 | m8xx.padir &= ~0x30; |
---|
553 | |
---|
554 | /* |
---|
555 | * Configure port C pins to enable RTS3 (static active low) |
---|
556 | */ |
---|
557 | m8xx.pcpar &= ~0x04; |
---|
558 | m8xx.pcso &= ~0x04; |
---|
559 | m8xx.pcdir |= 0x04; |
---|
560 | m8xx.pcdat &= ~0x04; |
---|
561 | break; |
---|
562 | case CONS_CHN_SCC4: |
---|
563 | /* |
---|
564 | * Configure port A pins to enable TXD4 and RXD4 pins |
---|
565 | * FIXME: add setup for modem control lines.... |
---|
566 | */ |
---|
567 | m8xx.papar |= 0xC0; |
---|
568 | m8xx.padir &= ~0xC0; |
---|
569 | |
---|
570 | /* |
---|
571 | * Configure port C pins to enable RTS4 pins (static active low) |
---|
572 | */ |
---|
573 | m8xx.pcpar &= ~0x08; |
---|
574 | m8xx.pcso &= ~0x08; |
---|
575 | m8xx.pcdir |= 0x08; |
---|
576 | m8xx.pcdat &= ~0x08; |
---|
577 | break; |
---|
578 | case CONS_CHN_SMC1: |
---|
579 | /* |
---|
580 | * Configure port B pins to enable SMTXD1 and SMRXD1 pins |
---|
581 | */ |
---|
582 | m8xx.pbpar |= 0xC0; |
---|
583 | m8xx.pbdir &= ~0xC0; |
---|
584 | break; |
---|
585 | case CONS_CHN_SMC2: |
---|
586 | /* |
---|
587 | * Configure port B pins to enable SMTXD2 and SMRXD2 pins |
---|
588 | */ |
---|
589 | m8xx.pbpar |= 0xC00; |
---|
590 | m8xx.pbdir &= ~0xC00; |
---|
591 | break; |
---|
592 | } |
---|
593 | /* |
---|
594 | * allocate and connect BRG |
---|
595 | */ |
---|
596 | sccBRGalloc(cd,9600); |
---|
597 | |
---|
598 | |
---|
599 | /* |
---|
600 | * Set up SCCx parameter RAM common to all protocols |
---|
601 | */ |
---|
602 | CHN_PARAM_SET(cd,rbase,(char *)cd->sccFrstRxBd - (char *)&m8xx); |
---|
603 | CHN_PARAM_SET(cd,tbase,(char *)cd->sccFrstTxBd - (char *)&m8xx); |
---|
604 | CHN_PARAM_SET(cd,rfcr ,M8xx_RFCR_MOT | M8xx_RFCR_DMA_SPACE(0)); |
---|
605 | CHN_PARAM_SET(cd,tfcr ,M8xx_TFCR_MOT | M8xx_TFCR_DMA_SPACE(0)); |
---|
606 | if (cd->mode != TERMIOS_POLLED) |
---|
607 | CHN_PARAM_SET(cd,mrblr,RXBUFSIZE); |
---|
608 | else |
---|
609 | CHN_PARAM_SET(cd,mrblr,1); |
---|
610 | |
---|
611 | /* |
---|
612 | * Set up SCCx parameter RAM UART-specific parameters |
---|
613 | */ |
---|
614 | CHN_PARAM_SET(cd,un.uart.max_idl ,MAX_IDL_DEFAULT); |
---|
615 | CHN_PARAM_SET(cd,un.uart.brkln ,0); |
---|
616 | CHN_PARAM_SET(cd,un.uart.brkec ,0); |
---|
617 | CHN_PARAM_SET(cd,un.uart.brkcr ,0); |
---|
618 | if (cd->is_scc) { |
---|
619 | cd->parms.sccp->un.uart.character[0]=0x8000; /* no char filter */ |
---|
620 | cd->parms.sccp->un.uart.rccm=0x80FF; /* control character mask */ |
---|
621 | } |
---|
622 | |
---|
623 | /* |
---|
624 | * Set up the Receive Buffer Descriptors |
---|
625 | */ |
---|
626 | for (i = 0;i < SCC_RXBD_CNT;i++) { |
---|
627 | cd->sccFrstRxBd[i].status = M8xx_BD_EMPTY | M8xx_BD_INTERRUPT; |
---|
628 | if (i == SCC_RXBD_CNT-1) { |
---|
629 | cd->sccFrstRxBd[i].status |= M8xx_BD_WRAP; |
---|
630 | } |
---|
631 | cd->sccFrstRxBd[i].length = 0; |
---|
632 | cd->sccFrstRxBd[i].buffer = (*cd->rxBuf)[i]; |
---|
633 | } |
---|
634 | /* |
---|
635 | * Setup the Transmit Buffer Descriptor |
---|
636 | */ |
---|
637 | for (i = 0;i < SCC_TXBD_CNT;i++) { |
---|
638 | cd->sccFrstTxBd[i].status = M8xx_BD_INTERRUPT; |
---|
639 | if (i == SCC_TXBD_CNT-1) { |
---|
640 | cd->sccFrstTxBd[i].status |= M8xx_BD_WRAP; |
---|
641 | } |
---|
642 | cd->sccFrstTxBd[i].length = 0; |
---|
643 | cd->sccFrstTxBd[i].buffer = NULL; |
---|
644 | } |
---|
645 | |
---|
646 | /* |
---|
647 | * Set up SCC general and protocol-specific mode registers |
---|
648 | */ |
---|
649 | CHN_EVENT_CLR(cd,~0); /* Clear any pending events */ |
---|
650 | CHN_MASK_SET(cd,0); /* Mask all interrupt/event sources */ |
---|
651 | |
---|
652 | if (cd->is_scc) { |
---|
653 | cd->regs.sccr->psmr = 0xb000; /* 8N1, CTS flow control */ |
---|
654 | cd->regs.sccr->gsmr_h = 0x00000000; |
---|
655 | cd->regs.sccr->gsmr_l = 0x00028004; /* UART mode */ |
---|
656 | } |
---|
657 | else { |
---|
658 | cd->regs.smcr->smcmr = 0x4820; |
---|
659 | } |
---|
660 | /* |
---|
661 | * Send "Init parameters" command |
---|
662 | */ |
---|
663 | m8xx_cp_execute_cmd(M8xx_CR_OP_INIT_RX_TX | cd->cr_chan_code); |
---|
664 | |
---|
665 | /* |
---|
666 | * Enable receiver and transmitter |
---|
667 | */ |
---|
668 | if (cd->is_scc) { |
---|
669 | cd->regs.sccr->gsmr_l |= 0x00000030; |
---|
670 | } |
---|
671 | else { |
---|
672 | cd->regs.smcr->smcmr |= 0x0003; |
---|
673 | } |
---|
674 | } |
---|
675 | |
---|
676 | /* |
---|
677 | * polled scc read function |
---|
678 | */ |
---|
679 | static int |
---|
680 | sccPollRead (rtems_termios_device_context *base) |
---|
681 | { |
---|
682 | m8xx_console_chan_desc_t *cd = (m8xx_console_chan_desc_t *)base; |
---|
683 | int c = -1; |
---|
684 | |
---|
685 | while(1) { |
---|
686 | if ((cd->sccCurrRxBd->status & M8xx_BD_EMPTY) != 0) { |
---|
687 | return -1; |
---|
688 | } |
---|
689 | |
---|
690 | if (0 == (cd->sccCurrRxBd->status & (M8xx_BD_OVERRUN |
---|
691 | | M8xx_BD_PARITY_ERROR |
---|
692 | | M8xx_BD_FRAMING_ERROR |
---|
693 | | M8xx_BD_BREAK |
---|
694 | | M8xx_BD_IDLE))) { |
---|
695 | /* character received and no error detected */ |
---|
696 | rtems_cache_invalidate_multiple_data_lines((void *)cd->sccCurrRxBd->buffer, |
---|
697 | cd->sccCurrRxBd->length); |
---|
698 | c = (unsigned)*((char *)cd->sccCurrRxBd->buffer); |
---|
699 | /* |
---|
700 | * clear status |
---|
701 | */ |
---|
702 | } |
---|
703 | cd->sccCurrRxBd->status = |
---|
704 | (cd->sccCurrRxBd->status |
---|
705 | & (M8xx_BD_WRAP | M8xx_BD_INTERRUPT)) |
---|
706 | | M8xx_BD_EMPTY; |
---|
707 | /* |
---|
708 | * advance to next BD |
---|
709 | */ |
---|
710 | if ((cd->sccCurrRxBd->status & M8xx_BD_WRAP) != 0) { |
---|
711 | cd->sccCurrRxBd = cd->sccFrstRxBd; |
---|
712 | } |
---|
713 | else { |
---|
714 | cd->sccCurrRxBd++; |
---|
715 | } |
---|
716 | if (c >= 0) { |
---|
717 | return c; |
---|
718 | } |
---|
719 | } |
---|
720 | } |
---|
721 | |
---|
722 | |
---|
723 | /* |
---|
724 | * Device-dependent write routine |
---|
725 | * Interrupt-driven devices: |
---|
726 | * Begin transmission of as many characters as possible (minimum is 1). |
---|
727 | * Polling devices: |
---|
728 | * Transmit all characters. |
---|
729 | */ |
---|
730 | static void |
---|
731 | sccInterruptWrite (rtems_termios_device_context *base, const char *buf, size_t len) |
---|
732 | { |
---|
733 | if (len > 0) { |
---|
734 | m8xx_console_chan_desc_t *cd = (m8xx_console_chan_desc_t *)base; |
---|
735 | if ((cd->sccPrepTxBd->status & M8xx_BD_READY) == 0) { |
---|
736 | cd->sccPrepTxBd->buffer = (char *)buf; |
---|
737 | cd->sccPrepTxBd->length = len; |
---|
738 | rtems_cache_flush_multiple_data_lines((const void *)buf,len); |
---|
739 | /* |
---|
740 | * clear status, set ready bit |
---|
741 | */ |
---|
742 | cd->sccPrepTxBd->status = |
---|
743 | (cd->sccPrepTxBd->status |
---|
744 | & M8xx_BD_WRAP) |
---|
745 | | M8xx_BD_READY | M8xx_BD_INTERRUPT; |
---|
746 | if ((cd->sccPrepTxBd->status & M8xx_BD_WRAP) != 0) { |
---|
747 | cd->sccPrepTxBd = cd->sccFrstTxBd; |
---|
748 | } |
---|
749 | else { |
---|
750 | cd->sccPrepTxBd++; |
---|
751 | } |
---|
752 | } |
---|
753 | } |
---|
754 | } |
---|
755 | |
---|
756 | static void |
---|
757 | sccPollWrite (rtems_termios_device_context *base, const char *buf, size_t len) |
---|
758 | { |
---|
759 | m8xx_console_chan_desc_t *cd = (m8xx_console_chan_desc_t *)base; |
---|
760 | static char txBuf[CONS_CHN_CNT][SCC_TXBD_CNT]; |
---|
761 | int chan = cd->chan; |
---|
762 | int bd_used; |
---|
763 | |
---|
764 | while (len--) { |
---|
765 | while (cd->sccPrepTxBd->status & M8xx_BD_READY) |
---|
766 | continue; |
---|
767 | bd_used = cd->sccPrepTxBd - cd->sccFrstTxBd; |
---|
768 | txBuf[chan][bd_used] = *buf++; |
---|
769 | rtems_cache_flush_multiple_data_lines((const void *)&txBuf[chan][bd_used], |
---|
770 | sizeof(txBuf[chan][bd_used])); |
---|
771 | cd->sccPrepTxBd->buffer = &(txBuf[chan][bd_used]); |
---|
772 | cd->sccPrepTxBd->length = 1; |
---|
773 | cd->sccPrepTxBd->status = |
---|
774 | (cd->sccPrepTxBd->status |
---|
775 | & M8xx_BD_WRAP) |
---|
776 | | M8xx_BD_READY; |
---|
777 | if ((cd->sccPrepTxBd->status & M8xx_BD_WRAP) != 0) { |
---|
778 | cd->sccPrepTxBd = cd->sccFrstTxBd; |
---|
779 | } |
---|
780 | else { |
---|
781 | cd->sccPrepTxBd++; |
---|
782 | } |
---|
783 | } |
---|
784 | } |
---|
785 | |
---|
786 | /* |
---|
787 | * printk basic support |
---|
788 | */ |
---|
789 | int BSP_output_chan = CONS_CHN_NONE; /* channel used for printk operation */ |
---|
790 | |
---|
791 | static void console_debug_putc_onlcr(const char c) |
---|
792 | { |
---|
793 | rtems_interrupt_level irq_level; |
---|
794 | |
---|
795 | if (BSP_output_chan != CONS_CHN_NONE) { |
---|
796 | rtems_interrupt_disable(irq_level); |
---|
797 | |
---|
798 | sccPollWrite (&m8xx_console_chan_desc[BSP_output_chan].base,&c,1); |
---|
799 | rtems_interrupt_enable(irq_level); |
---|
800 | } |
---|
801 | } |
---|
802 | |
---|
803 | BSP_output_char_function_type BSP_output_char = console_debug_putc_onlcr; |
---|
804 | BSP_polling_getchar_function_type BSP_poll_char = NULL; |
---|
805 | |
---|
806 | |
---|
807 | /* |
---|
808 | *************** |
---|
809 | * BOILERPLATE * |
---|
810 | *************** |
---|
811 | */ |
---|
812 | |
---|
813 | struct { |
---|
814 | rtems_device_minor_number minor; |
---|
815 | int driver_mode; |
---|
816 | } channel_list[] = { |
---|
817 | {CONS_CHN_SMC1,CONS_SMC1_MODE}, |
---|
818 | {CONS_CHN_SMC2,CONS_SMC2_MODE}, |
---|
819 | {CONS_CHN_SCC1,CONS_SCC1_MODE}, |
---|
820 | {CONS_CHN_SCC2,CONS_SCC2_MODE}, |
---|
821 | {CONS_CHN_SCC3,CONS_SCC3_MODE}, |
---|
822 | {CONS_CHN_SCC4,CONS_SCC4_MODE} |
---|
823 | }; |
---|
824 | |
---|
825 | static bool m8xx_console_first_open( |
---|
826 | rtems_termios_tty *tty, |
---|
827 | rtems_termios_device_context *base, |
---|
828 | struct termios *term, |
---|
829 | rtems_libio_open_close_args_t *args |
---|
830 | ) |
---|
831 | { |
---|
832 | m8xx_console_chan_desc_t *cd = (m8xx_console_chan_desc_t *)base; |
---|
833 | |
---|
834 | if (cd->mode == TERMIOS_IRQ_DRIVEN) { |
---|
835 | rtems_status_code sc; |
---|
836 | |
---|
837 | sc = rtems_interrupt_handler_install( |
---|
838 | cd->ivec_src, |
---|
839 | "SCC", |
---|
840 | RTEMS_INTERRUPT_UNIQUE, |
---|
841 | sccInterruptHandler, |
---|
842 | tty |
---|
843 | ); |
---|
844 | if (sc != RTEMS_SUCCESSFUL) { |
---|
845 | return false; |
---|
846 | } |
---|
847 | |
---|
848 | mpc8xx_console_irq_on(cd); |
---|
849 | } |
---|
850 | |
---|
851 | return true; |
---|
852 | } |
---|
853 | |
---|
854 | static const rtems_termios_device_handler m8xx_console_handler_polled = { |
---|
855 | .first_open = m8xx_console_first_open, |
---|
856 | .set_attributes = sccSetAttributes, |
---|
857 | .write = sccPollWrite, |
---|
858 | .poll_read = sccPollRead, |
---|
859 | .mode = TERMIOS_POLLED |
---|
860 | }; |
---|
861 | |
---|
862 | static const rtems_termios_device_handler m8xx_console_handler_irq_driven = { |
---|
863 | .first_open = m8xx_console_first_open, |
---|
864 | .set_attributes = sccSetAttributes, |
---|
865 | .write = sccInterruptWrite, |
---|
866 | .mode = TERMIOS_IRQ_DRIVEN |
---|
867 | }; |
---|
868 | |
---|
869 | /* |
---|
870 | * Initialize and register the device |
---|
871 | */ |
---|
872 | rtems_device_driver console_initialize(rtems_device_major_number major, |
---|
873 | rtems_device_minor_number minor,/* ignored */ |
---|
874 | void *arg |
---|
875 | ) |
---|
876 | { |
---|
877 | rtems_status_code status = RTEMS_SUCCESSFUL; |
---|
878 | int entry,ttynum; |
---|
879 | char tty_name[] = "/dev/tty00"; |
---|
880 | |
---|
881 | /* |
---|
882 | * Set up TERMIOS |
---|
883 | */ |
---|
884 | rtems_termios_initialize (); |
---|
885 | /* |
---|
886 | * init BRG allocataion |
---|
887 | */ |
---|
888 | sccBRGinit(); |
---|
889 | ttynum = 0; |
---|
890 | for (entry = 0; |
---|
891 | (entry < sizeof(channel_list)/sizeof(channel_list[0])) |
---|
892 | && (status == RTEMS_SUCCESSFUL); |
---|
893 | entry++) { |
---|
894 | if (channel_list[entry].driver_mode != CONS_MODE_UNUSED) { |
---|
895 | m8xx_console_chan_desc_t *cd = |
---|
896 | &m8xx_console_chan_desc[channel_list[entry].minor]; |
---|
897 | /* |
---|
898 | * Do device-specific initialization |
---|
899 | */ |
---|
900 | cd->mode = channel_list[entry].driver_mode; |
---|
901 | sccInitialize (cd); |
---|
902 | |
---|
903 | /* |
---|
904 | * build device name |
---|
905 | */ |
---|
906 | tty_name[sizeof(tty_name)-2] = '0'+ttynum; |
---|
907 | ttynum++; |
---|
908 | /* |
---|
909 | * Register the device |
---|
910 | */ |
---|
911 | status = rtems_termios_device_install( |
---|
912 | tty_name, |
---|
913 | cd->mode == TERMIOS_IRQ_DRIVEN ? |
---|
914 | &m8xx_console_handler_irq_driven : &m8xx_console_handler_polled, |
---|
915 | NULL, |
---|
916 | &cd->base |
---|
917 | ); |
---|
918 | if (status != RTEMS_SUCCESSFUL) { |
---|
919 | rtems_fatal_error_occurred (status); |
---|
920 | } |
---|
921 | |
---|
922 | if (cd->chan == CONSOLE_CHN) { |
---|
923 | int rv; |
---|
924 | |
---|
925 | rv = link(tty_name, CONSOLE_DEVICE_NAME); |
---|
926 | if (rv != 0) { |
---|
927 | rtems_fatal_error_occurred (RTEMS_IO_ERROR); |
---|
928 | } |
---|
929 | } |
---|
930 | } |
---|
931 | } |
---|
932 | |
---|
933 | /* |
---|
934 | * enable printk support |
---|
935 | */ |
---|
936 | BSP_output_chan = PRINTK_CHN; |
---|
937 | |
---|
938 | return RTEMS_SUCCESSFUL; |
---|
939 | } |
---|