source: rtems/bsps/powerpc/t32mppc/start/start.S @ e9f15be

5
Last change on this file since e9f15be was 511dc4b, checked in by Sebastian Huber <sebastian.huber@…>, on 06/19/18 at 07:09:51

Rework initialization and interrupt stack support

Statically initialize the interrupt stack area
(_Configuration_Interrupt_stack_area_begin,
_Configuration_Interrupt_stack_area_end, and
_Configuration_Interrupt_stack_size) via <rtems/confdefs.h>. Place the
interrupt stack area in a special section ".rtemsstack.interrupt". Let
BSPs define the optimal placement of this section in their linker
command files (e.g. in a fast on-chip memory).

This change makes makes the CPU_HAS_SOFTWARE_INTERRUPT_STACK and
CPU_HAS_HARDWARE_INTERRUPT_STACK CPU port defines superfluous, since the
low level initialization code has all information available via global
symbols.

This change makes the CPU_ALLOCATE_INTERRUPT_STACK CPU port define
superfluous, since the interrupt stacks are allocated by confdefs.h for
all architectures. There is no need for BSP-specific linker command
file magic (except the section placement), see previous ARM linker
command file as a bad example.

Remove _CPU_Install_interrupt_stack(). Initialize the hardware
interrupt stack in _CPU_Initialize() if necessary (e.g.
m68k_install_interrupt_stack()).

The optional _CPU_Interrupt_stack_setup() is still useful to customize
the registration of the interrupt stack area in the per-CPU information.

The initialization stack can reuse the interrupt stack, since

  • interrupts are disabled during the sequential system initialization, and
  • the boot_card() function does not return.

This stack resuse saves memory.

Changes per architecture:

arm:

  • Mostly replace the linker symbol based configuration of stacks with the standard <rtems/confdefs.h> configuration via CONFIGURE_INTERRUPT_STACK_SIZE. The size of the FIQ, ABT and UND mode stack is still defined via linker symbols. These modes are rarely used in applications and the default values provided by the BSP should be sufficient in most cases.
  • Remove the bsp_processor_count linker symbol hack used for the SMP support. This is possible since the interrupt stack area is now allocated by the linker and not allocated from the heap. This makes some configure.ac stuff obsolete. Remove the now superfluous BSP variants altcycv_devkit_smp and realview_pbx_a9_qemu_smp.

bfin:

  • Remove unused magic linker command file allocation of initialization stack. Maybe a previous linker command file copy and paste problem? In the start.S the initialization stack is set to a hard coded value.

lm32, m32c, mips, nios2, riscv, sh, v850:

  • Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack.

m68k:

  • Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack.

powerpc:

  • Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack.
  • Used dedicated memory region (REGION_RTEMSSTACK) for the interrupt stack on BSPs using the shared linkcmds.base (replacement for REGION_RWEXTRA).

sparc:

  • Remove the hard coded initialization stack. Use the interrupt stack for the initialization stack on the boot processor. This saves 16KiB of RAM.

Update #3459.
  • Property mode set to 100644
File size: 4.7 KB
Line 
1/*
2 * Copyright (c) 2012, 2017 embedded brains GmbH.  All rights reserved.
3 *
4 *  embedded brains GmbH
5 *  Dornierstr. 4
6 *  82178 Puchheim
7 *  Germany
8 *  <rtems@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.org/license/LICENSE.
13 */
14
15#include <bspopts.h>
16
17#include <rtems/score/percpu.h>
18#include <libcpu/powerpc-utility.h>
19#include <bsp/vectors.h>
20
21        .globl _start
22        .globl bsp_exc_vector_base
23
24        .section ".bsp_start_text", "ax"
25
26        /* Primitive NULL pointer protection */
27.rept 1024
28        sc
29.endr
30
31_start:
32        /* Enable time base */
33        li      r0, 0x4000
34        mtspr   HID0, r0
35
36        /* Initialize start stack */
37        LA      r1, _Configuration_Interrupt_stack_area_end
38        subi    r1, r1, 16
39        li      r0, 0
40        stw     r0, 0(r1)
41
42        SET_SELF_CPU_CONTROL    r3, r4
43
44        /* Copy fast text */
45        LWI     r3, bsp_section_fast_text_begin
46        LWI     r4, bsp_section_fast_text_load_begin
47        LWI     r5, bsp_section_fast_text_size
48        bl      copy
49
50        /* Copy read-only data */
51        LWI     r3, bsp_section_rodata_begin
52        LWI     r4, bsp_section_rodata_load_begin
53        LWI     r5, bsp_section_rodata_size
54        bl      copy
55
56        /* Copy fast data */
57        LWI     r3, bsp_section_fast_data_begin
58        LWI     r4, bsp_section_fast_data_load_begin
59        LWI     r5, bsp_section_fast_data_size
60        bl      copy
61
62        /* Copy data */
63        LWI     r3, bsp_section_data_begin
64        LWI     r4, bsp_section_data_load_begin
65        LWI     r5, bsp_section_data_size
66        bl      copy
67
68        /* Clear SBSS */
69        LWI     r3, bsp_section_sbss_begin
70        LWI     r4, bsp_section_sbss_size
71        bl      bsp_start_zero
72
73        /* Clear BSS */
74        LWI     r3, bsp_section_bss_begin
75        LWI     r4, bsp_section_bss_size
76        bl      bsp_start_zero
77
78        /* Set up EABI and SYSV environment */
79        bl      __eabi
80
81        /* Clear command line */
82        li      r3, 0
83
84        bl      boot_card
85
86twiddle:
87        b       twiddle
88
89copy:
90        cmpw    r3, r4
91        beqlr
92        b       memcpy
93
94        /* Exception vector prologues area */
95        .section ".bsp_start_text", "ax"
96        .align 4
97bsp_exc_vector_base:
98        /* Critical input */
99        PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
100        PPC_REG_STORE   r3, GPR3_OFFSET(r1)
101        li      r3, 0
102        b       ppc_exc_fatal_critical
103        /* Machine check */
104        PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
105        PPC_REG_STORE   r3, GPR3_OFFSET(r1)
106        li      r3, 1
107        b       ppc_exc_fatal_machine_check
108        /* Data storage */
109        PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
110        PPC_REG_STORE   r3, GPR3_OFFSET(r1)
111        li      r3, 2
112        b       ppc_exc_fatal_normal
113        /* Instruction storage */
114        PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
115        PPC_REG_STORE   r3, GPR3_OFFSET(r1)
116        li      r3, 3
117        b       ppc_exc_fatal_normal
118        /* External input */
119        PPC_REG_STORE_UPDATE    r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1)
120        PPC_REG_STORE   r3, GPR3_OFFSET(r1)
121        li      r3, 4
122        b       ppc_exc_interrupt
123        /* Alignment */
124        PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
125        PPC_REG_STORE   r3, GPR3_OFFSET(r1)
126        li      r3, 5
127        b       ppc_exc_fatal_normal
128        /* Program */
129        PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
130        PPC_REG_STORE   r3, GPR3_OFFSET(r1)
131        li      r3, 6
132        b       ppc_exc_fatal_normal
133        /* Floating-point unavailable */
134        PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
135        PPC_REG_STORE   r3, GPR3_OFFSET(r1)
136        li      r3, 7
137        b       ppc_exc_fatal_normal
138        /* System call */
139        PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
140        PPC_REG_STORE   r3, GPR3_OFFSET(r1)
141        li      r3, 8
142        b       ppc_exc_fatal_normal
143        /* APU unavailable */
144        PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
145        PPC_REG_STORE   r3, GPR3_OFFSET(r1)
146        li      r3, 9
147        b       ppc_exc_fatal_normal
148        /* Decrementer */
149        PPC_REG_STORE_UPDATE    r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1)
150        PPC_REG_STORE   r3, PPC_EXC_GPR3_PROLOGUE_OFFSET(r1)
151        li      r3, 10
152        b       ppc_exc_interrupt
153        /* Fixed-interval timer interrupt */
154        PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
155        PPC_REG_STORE   r3, GPR3_OFFSET(r1)
156        li      r3, 11
157        b       ppc_exc_fatal_normal
158        /* Watchdog timer interrupt */
159        PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
160        PPC_REG_STORE   r3, GPR3_OFFSET(r1)
161        li      r3, 12
162        b       ppc_exc_fatal_critical
163        /* Data TLB error */
164        PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
165        PPC_REG_STORE   r3, GPR3_OFFSET(r1)
166        li      r3, 13
167        b       ppc_exc_fatal_normal
168        /* Instruction TLB error */
169        PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
170        PPC_REG_STORE   r3, GPR3_OFFSET(r1)
171        li      r3, 14
172        b       ppc_exc_fatal_normal
173        /* Debug */
174        PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
175        PPC_REG_STORE   r3, GPR3_OFFSET(r1)
176        li      r3, 15
177        b       ppc_exc_fatal_debug
178        /* SPE APU unavailable or AltiVec unavailable */
179        PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
180        PPC_REG_STORE   r3, GPR3_OFFSET(r1)
181        li      r3, 32
182        b       ppc_exc_fatal_normal
183        /* SPE floating-point data exception or AltiVec assist */
184        PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
185        PPC_REG_STORE   r3, GPR3_OFFSET(r1)
186        li      r3, 33
187        b       ppc_exc_fatal_normal
188        /* SPE floating-point round exception */
189        PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
190        PPC_REG_STORE   r3, GPR3_OFFSET(r1)
191        li      r3, 34
192        b       ppc_exc_fatal_normal
193        /* Performance monitor */
194        PPC_REG_STORE_UPDATE    r1, -EXC_GENERIC_SIZE(r1)
195        PPC_REG_STORE   r3, GPR3_OFFSET(r1)
196        li      r3, 35
197        b       ppc_exc_fatal_normal
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