1 | /* |
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2 | * Copyright (c) 2012, 2017 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * embedded brains GmbH |
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5 | * Dornierstr. 4 |
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6 | * 82178 Puchheim |
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7 | * Germany |
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8 | * <rtems@embedded-brains.de> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #include <rtems/config.h> |
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16 | #include <rtems/counter.h> |
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17 | |
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18 | #include <bsp.h> |
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19 | #include <bsp/vectors.h> |
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20 | #include <bsp/bootcard.h> |
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21 | #include <bsp/irq-generic.h> |
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22 | #include <bsp/linker-symbols.h> |
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23 | |
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24 | LINKER_SYMBOL(bsp_exc_vector_base); |
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25 | |
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26 | /* |
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27 | * Configuration parameter for clock driver. The Trace32 PowerPC simulator has |
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28 | * an odd decrementer frequency. The time base frequency is one tick per |
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29 | * instruction. The decrementer frequency is one tick per ten instructions. |
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30 | * The clock driver assumes that the time base and decrementer frequencies are |
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31 | * equal. For now we simulate processor that issues 10000000 instructions per |
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32 | * second. |
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33 | */ |
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34 | uint32_t bsp_time_base_frequency = 10000000; |
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35 | |
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36 | #define MTIVPR(base) \ |
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37 | __asm__ volatile ("mtivpr %0" : : "r" (base)) |
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38 | |
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39 | #define VECTOR_TABLE_ENTRY_SIZE 16 |
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40 | |
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41 | #define MTIVOR(vec, offset) \ |
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42 | do { \ |
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43 | __asm__ volatile ("mtspr " RTEMS_XSTRING(vec) ", %0" : : "r" (offset)); \ |
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44 | offset += VECTOR_TABLE_ENTRY_SIZE; \ |
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45 | } while (0) |
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46 | |
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47 | static void t32mppc_initialize_exceptions(void) |
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48 | { |
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49 | uintptr_t addr; |
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50 | |
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51 | ppc_exc_initialize_interrupt_stack( |
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52 | (uintptr_t) _ISR_Stack_area_begin |
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53 | ); |
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54 | |
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55 | addr = (uintptr_t) bsp_exc_vector_base; |
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56 | MTIVPR(addr); |
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57 | MTIVOR(BOOKE_IVOR0, addr); |
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58 | MTIVOR(BOOKE_IVOR1, addr); |
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59 | MTIVOR(BOOKE_IVOR2, addr); |
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60 | MTIVOR(BOOKE_IVOR3, addr); |
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61 | MTIVOR(BOOKE_IVOR4, addr); |
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62 | MTIVOR(BOOKE_IVOR5, addr); |
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63 | MTIVOR(BOOKE_IVOR6, addr); |
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64 | MTIVOR(BOOKE_IVOR7, addr); |
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65 | MTIVOR(BOOKE_IVOR8, addr); |
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66 | MTIVOR(BOOKE_IVOR9, addr); |
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67 | MTIVOR(BOOKE_IVOR10, addr); |
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68 | MTIVOR(BOOKE_IVOR11, addr); |
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69 | MTIVOR(BOOKE_IVOR12, addr); |
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70 | MTIVOR(BOOKE_IVOR13, addr); |
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71 | MTIVOR(BOOKE_IVOR14, addr); |
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72 | MTIVOR(BOOKE_IVOR15, addr); |
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73 | MTIVOR(BOOKE_IVOR32, addr); |
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74 | MTIVOR(BOOKE_IVOR33, addr); |
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75 | MTIVOR(BOOKE_IVOR34, addr); |
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76 | MTIVOR(BOOKE_IVOR35, addr); |
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77 | } |
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78 | |
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79 | uint32_t _CPU_Counter_frequency(void) |
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80 | { |
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81 | return bsp_time_base_frequency; |
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82 | } |
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83 | |
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84 | void bsp_start(void) |
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85 | { |
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86 | get_ppc_cpu_type(); |
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87 | get_ppc_cpu_revision(); |
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88 | t32mppc_initialize_exceptions(); |
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89 | bsp_interrupt_initialize(); |
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90 | } |
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