1 | /* |
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2 | * Intec SS555 initialization routines. |
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3 | */ |
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4 | |
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5 | /* |
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6 | * SS555 port sponsored by Defence Research and Development Canada - Suffield |
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7 | * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) |
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8 | * |
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9 | * Derived from c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c: |
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10 | * |
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11 | * Copyright (c) 1999, National Research Council of Canada |
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12 | * |
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13 | * The license and distribution terms for this file may be |
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14 | * found in the file LICENSE in this distribution or at |
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15 | * http://www.rtems.org/license/LICENSE. |
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16 | */ |
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17 | |
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18 | #include <bsp.h> |
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19 | |
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20 | SPR_RW(ICTRL); |
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21 | SPR_RW(PPC_DEC); |
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22 | SPR_RW(TBWU); |
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23 | SPR_RW(TBWL); |
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24 | SPR_RO(IMMR); |
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25 | SPR_RW(MI_GRA); |
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26 | SPR_RW(L2U_GRA); |
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27 | SPR_RW(BBCMCR); |
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28 | |
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29 | extern char int_ram_top[]; /* top of internal ram */ |
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30 | |
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31 | /* |
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32 | * Initialize SS555 |
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33 | */ |
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34 | void _InitSS555 (void) |
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35 | { |
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36 | register uint32_t plprcr, msr; |
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37 | |
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38 | /* |
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39 | * Initialize the System Protection Control Register (SYPCR). |
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40 | * The SYPCR can only be written once after Reset. |
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41 | */ |
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42 | usiu.sypcr = |
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43 | USIU_SYPCR_SWTC(WATCHDOG_TIMEOUT) /* set watchdog timeout */ |
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44 | | USIU_SYPCR_BMT(0xFF) /* set bus monitor timeout */ |
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45 | | USIU_SYPCR_BME /* enable bus monitor */ |
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46 | | USIU_SYPCR_SWF /* watchdog halted in freeze */ |
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47 | #if WATCHDOG_TIMEOUT != 0xFFFF |
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48 | | USIU_SYPCR_SWE /* enable watchdog */ |
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49 | #endif |
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50 | | USIU_SYPCR_SWRI /* watchdog forces reset */ |
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51 | | USIU_SYPCR_SWP; /* prescale watchdog by 2048 */ |
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52 | |
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53 | TICKLE_WATCHDOG(); /* restart watchdog timer */ |
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54 | |
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55 | /* |
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56 | * Re-tune the PLL to the desired system clock frequency. |
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57 | */ |
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58 | usiu.plprck = USIU_UNLOCK_KEY; /* unlock PLPRCR */ |
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59 | usiu.plprcr = |
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60 | USIU_PLPRCR_TEXPS /* assert TEXP always */ |
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61 | | USIU_PLPRCR_MF(BSP_CLOCK_HZ / BSP_CRYSTAL_HZ); |
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62 | /* PLL multiplication factor */ |
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63 | usiu.plprck = 0; /* lock PLPRCR */ |
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64 | |
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65 | while (((plprcr = usiu.plprcr) & USIU_PLPRCR_SPLS) == 0) |
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66 | ; /* wait for PLL to re-lock */ |
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67 | |
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68 | /* |
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69 | * Enable the timebase and decrementer, then initialize decrementer |
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70 | * register to a large value to guarantee that a decrementer interrupt |
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71 | * will not be generated before the kernel is fully initialized. |
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72 | * Initialize the timebase register to zero. |
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73 | */ |
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74 | usiu.tbscrk = USIU_UNLOCK_KEY; |
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75 | usiu.tbscr |= USIU_TBSCR_TBE; /* enable time base and decrementer */ |
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76 | usiu.tbscrk = 0; |
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77 | |
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78 | usiu.tbk = USIU_UNLOCK_KEY; |
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79 | _write_PPC_DEC(0x7FFFFFFF); |
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80 | _write_TBWU(0x00000000 ); |
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81 | _write_TBWL(0x00000000 ); |
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82 | usiu.tbk = 0; |
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83 | |
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84 | /* |
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85 | * Run the Inter-Module Bus at full speed. |
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86 | */ |
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87 | imb.uimb.umcr &= ~UIMB_UMCR_HSPEED; |
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88 | |
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89 | /* |
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90 | * Initialize Memory Controller for External RAM |
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91 | * |
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92 | * Initialize the Base and Option Registers (BR0-BR7 and OR0-OR7). Note |
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93 | * that for all chip selects, ORx should be programmed before BRx. |
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94 | * |
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95 | * If booting from internal flash ROM, configure the external RAM to |
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96 | * extend the internal RAM. If booting from external RAM, leave it at |
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97 | * zero but set it up appropriately. |
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98 | */ |
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99 | usiu.memc[0]._or = |
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100 | USIU_MEMC_OR_512K /* bank size */ |
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101 | | USIU_MEMC_OR_SCY(0) /* wait states in first beat of burst */ |
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102 | | USIU_MEMC_OR_BSCY(0); /* wait states in subsequent beats */ |
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103 | |
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104 | usiu.memc[0]._br = |
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105 | USIU_MEMC_BR_BA(_read_IMMR() & IMMR_FLEN |
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106 | ? (uint32_t)int_ram_top : 0) /* base address */ |
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107 | | USIU_MEMC_BR_PS32 /* 32-bit data bus */ |
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108 | | USIU_MEMC_BR_TBDIP /* toggle bdip */ |
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109 | | USIU_MEMC_BR_V; /* base register valid */ |
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110 | |
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111 | /* |
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112 | * Initialize Memory Controller for External CPLD |
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113 | * |
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114 | * The SS555 board includes a CPLD to control on-board features and |
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115 | * off-board devices. (Configuration taken from Intec's hwhook.c) |
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116 | */ |
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117 | usiu.memc[3]._or = |
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118 | USIU_MEMC_OR_16M /* bank size */ |
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119 | | USIU_MEMC_OR_CSNT /* negate CS/WE early */ |
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120 | | USIU_MEMC_OR_ACS_HALF /* assert CS half cycle after address */ |
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121 | | USIU_MEMC_OR_SCY(15) /* wait states in first beat of burst */ |
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122 | | USIU_MEMC_OR_TRLX; /* relaxed timing */ |
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123 | |
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124 | usiu.memc[3]._br = |
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125 | USIU_MEMC_BR_BA(&cpld) /* base address */ |
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126 | | USIU_MEMC_BR_PS16 /* 16-bit data bus */ |
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127 | | USIU_MEMC_BR_BI /* inhibit bursting */ |
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128 | | USIU_MEMC_BR_V; /* base register valid */ |
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129 | |
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130 | /* |
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131 | * Disable show cycles and serialization so that burst accesses will work |
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132 | * properly. A different value, such as 0x0, may be more appropriate for |
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133 | * debugging, but can be set with the debugger, if needed. |
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134 | */ |
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135 | _write_ICTRL(0x00000007); |
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136 | |
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137 | /* |
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138 | * Set up Burst Buffer Controller (BBC) |
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139 | */ |
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140 | _write_BBCMCR( |
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141 | BBCMCR_ETRE /* enable exception relocation */ |
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142 | | BBCMCR_BE); /* enable burst accesses */ |
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143 | _isync; |
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144 | |
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145 | _CPU_MSR_GET(msr); |
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146 | msr |= MSR_IP; /* set prefix for exception relocation */ |
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147 | _CPU_MSR_SET(msr); |
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148 | } |
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