source: rtems/bsps/powerpc/ss555/start/iss555.c @ 511dc4b

5
Last change on this file since 511dc4b was 9964895, checked in by Sebastian Huber <sebastian.huber@…>, on Apr 20, 2018 at 8:35:35 AM

bsps: Move startup files to bsps

Adjust build support files to new directory layout.

This patch is a part of the BSP source reorganization.

Update #3285.

  • Property mode set to 100644
File size: 4.5 KB
Line 
1/*
2 *  Intec SS555 initialization routines.
3 */
4
5/*
6 *  SS555 port sponsored by Defence Research and Development Canada - Suffield
7 *  Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
8 *
9 *  Derived from c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c:
10 *
11 *  Copyright (c) 1999, National Research Council of Canada
12 *
13 *  The license and distribution terms for this file may be
14 *  found in the file LICENSE in this distribution or at
15 *  http://www.rtems.org/license/LICENSE.
16 */
17
18#include <bsp.h>
19
20SPR_RW(ICTRL);
21SPR_RW(PPC_DEC);
22SPR_RW(TBWU);
23SPR_RW(TBWL);
24SPR_RO(IMMR);
25SPR_RW(MI_GRA);
26SPR_RW(L2U_GRA);
27SPR_RW(BBCMCR);
28
29extern char int_ram_top[];              /* top of internal ram */
30
31/*
32 *  Initialize SS555
33 */
34void _InitSS555 (void)
35{
36  register uint32_t plprcr, msr;
37
38  /*
39   * Initialize the System Protection Control Register (SYPCR).
40   * The SYPCR can only be written once after Reset.
41   */
42  usiu.sypcr =
43      USIU_SYPCR_SWTC(WATCHDOG_TIMEOUT) /* set watchdog timeout */
44    | USIU_SYPCR_BMT(0xFF)              /* set bus monitor timeout */
45    | USIU_SYPCR_BME                    /* enable bus monitor */
46    | USIU_SYPCR_SWF                    /* watchdog halted in freeze */
47#if WATCHDOG_TIMEOUT != 0xFFFF
48    | USIU_SYPCR_SWE                    /* enable watchdog */
49#endif
50    | USIU_SYPCR_SWRI                   /* watchdog forces reset */
51    | USIU_SYPCR_SWP;                   /* prescale watchdog by 2048 */
52
53  TICKLE_WATCHDOG();                    /* restart watchdog timer */
54
55  /*
56   * Re-tune the PLL to the desired system clock frequency.
57   */
58  usiu.plprck = USIU_UNLOCK_KEY;        /* unlock PLPRCR */
59  usiu.plprcr =
60      USIU_PLPRCR_TEXPS                 /* assert TEXP always */
61    | USIU_PLPRCR_MF(BSP_CLOCK_HZ / BSP_CRYSTAL_HZ);
62                                        /* PLL multiplication factor */
63  usiu.plprck = 0;                      /* lock PLPRCR */
64
65  while (((plprcr = usiu.plprcr) & USIU_PLPRCR_SPLS) == 0)
66    ;                                   /* wait for PLL to re-lock */
67
68  /*
69   * Enable the timebase and decrementer, then initialize decrementer
70   * register to a large value to guarantee that a decrementer interrupt
71   * will not be generated before the kernel is fully initialized.
72   * Initialize the timebase register to zero.
73   */
74  usiu.tbscrk = USIU_UNLOCK_KEY;
75  usiu.tbscr |= USIU_TBSCR_TBE;         /* enable time base and decrementer */
76  usiu.tbscrk = 0;
77
78  usiu.tbk = USIU_UNLOCK_KEY;
79  _write_PPC_DEC(0x7FFFFFFF);
80  _write_TBWU(0x00000000 );
81  _write_TBWL(0x00000000 );
82  usiu.tbk = 0;
83
84  /*
85   * Run the Inter-Module Bus at full speed.
86   */
87  imb.uimb.umcr &= ~UIMB_UMCR_HSPEED;
88
89  /*
90   * Initialize Memory Controller for External RAM
91   *
92   * Initialize the Base and Option Registers (BR0-BR7 and OR0-OR7).  Note
93   * that for all chip selects, ORx should be programmed before BRx.
94   *
95   * If booting from internal flash ROM, configure the external RAM to
96   * extend the internal RAM.  If booting from external RAM, leave it at
97   * zero but set it up appropriately.
98   */
99  usiu.memc[0]._or =
100      USIU_MEMC_OR_512K                 /* bank size */
101    | USIU_MEMC_OR_SCY(0)               /* wait states in first beat of burst */
102    | USIU_MEMC_OR_BSCY(0);             /* wait states in subsequent beats */
103
104  usiu.memc[0]._br =
105      USIU_MEMC_BR_BA(_read_IMMR() & IMMR_FLEN
106        ? (uint32_t)int_ram_top : 0)    /* base address */
107    | USIU_MEMC_BR_PS32                 /* 32-bit data bus */
108    | USIU_MEMC_BR_TBDIP                /* toggle bdip */
109    | USIU_MEMC_BR_V;                   /* base register valid */
110
111  /*
112   * Initialize Memory Controller for External CPLD
113   *
114   * The SS555 board includes a CPLD to control on-board features and
115   * off-board devices.  (Configuration taken from Intec's hwhook.c)
116   */
117  usiu.memc[3]._or =
118      USIU_MEMC_OR_16M                  /* bank size */
119    | USIU_MEMC_OR_CSNT                 /* negate CS/WE early */
120    | USIU_MEMC_OR_ACS_HALF             /* assert CS half cycle after address */
121    | USIU_MEMC_OR_SCY(15)              /* wait states in first beat of burst */
122    | USIU_MEMC_OR_TRLX;                /* relaxed timing */
123
124  usiu.memc[3]._br =
125      USIU_MEMC_BR_BA(&cpld)            /* base address */
126    | USIU_MEMC_BR_PS16                 /* 16-bit data bus */
127    | USIU_MEMC_BR_BI                   /* inhibit bursting */
128    | USIU_MEMC_BR_V;                   /* base register valid */
129
130  /*
131   * Disable show cycles and serialization so that burst accesses will work
132   * properly.  A different value, such as 0x0, may be more appropriate for
133   * debugging, but can be set with the debugger, if needed.
134   */
135  _write_ICTRL(0x00000007);
136
137  /*
138   * Set up Burst Buffer Controller (BBC)
139   */
140  _write_BBCMCR(
141      BBCMCR_ETRE                       /* enable exception relocation */
142    | BBCMCR_BE);                       /* enable burst accesses */
143  _isync;
144
145  _CPU_MSR_GET(msr);
146  msr |= MSR_IP;                /* set prefix for exception relocation */
147  _CPU_MSR_SET(msr);
148}
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