1 | /* |
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2 | * irq_init.c |
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3 | * |
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4 | * This file contains the implementation of rtems initialization |
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5 | * related to interrupt handling. |
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6 | */ |
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7 | |
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8 | /* |
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9 | * MPC5xx port sponsored by Defence Research and Development Canada - Suffield |
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10 | * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) |
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11 | * |
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12 | * Derived from libbsp/powerpc/mbx8xx/irq/irq_init.c: |
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13 | * |
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14 | * CopyRight (C) 2001 valette@crf.canon.fr |
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15 | * |
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16 | * The license and distribution terms for this file may be |
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17 | * found in the file LICENSE in this distribution or at |
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18 | * http://www.rtems.org/license/LICENSE. |
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19 | */ |
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20 | |
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21 | #include <rtems.h> |
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22 | #include <mpc5xx.h> |
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23 | #include <libcpu/vectors.h> |
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24 | #include <libcpu/raw_exception.h> |
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25 | #include <bsp/irq.h> |
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26 | |
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27 | extern rtems_exception_handler_t dispatch_irq_handler; |
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28 | |
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29 | volatile unsigned int ppc_cached_irq_mask; |
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30 | |
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31 | /* |
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32 | * default methods |
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33 | */ |
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34 | static void nop_hdl(rtems_irq_hdl_param ignored) |
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35 | { |
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36 | } |
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37 | |
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38 | static void nop_irq_enable(const struct __rtems_irq_connect_data__*ignored) |
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39 | { |
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40 | } |
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41 | |
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42 | static void nop_raw_enable( |
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43 | const struct __rtems_raw_except_connect_data__*ignored |
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44 | ) |
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45 | { |
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46 | } |
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47 | |
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48 | static int irq_is_connected(const struct __rtems_irq_connect_data__*ignored) |
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49 | { |
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50 | return 0; |
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51 | } |
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52 | |
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53 | static int raw_is_connected(const struct __rtems_raw_except_connect_data__*ignored) |
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54 | { |
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55 | return 0; |
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56 | } |
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57 | |
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58 | static rtems_irq_connect_data rtemsIrq[CPU_IRQ_COUNT]; |
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59 | static rtems_irq_global_settings initial_config; |
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60 | static rtems_irq_connect_data defaultIrq = { |
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61 | 0, /* vector */ |
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62 | nop_hdl, /* hdl */ |
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63 | NULL, /* handle */ |
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64 | nop_irq_enable, /* on */ |
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65 | nop_irq_enable, /* off */ |
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66 | irq_is_connected /* isOn */ |
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67 | }; |
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68 | |
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69 | static rtems_irq_prio irqPrioTable[CPU_IRQ_COUNT]={ |
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70 | /* |
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71 | * actual priorities for interrupt : |
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72 | * 0 means that only current interrupt is masked |
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73 | * 255 means all other interrupts are masked |
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74 | */ |
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75 | /* |
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76 | * USIU interrupts. |
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77 | */ |
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78 | 7,7, 6,6, 5,5, 4,4, 3,3, 2,2, 1,1, 0,0, |
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79 | /* |
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80 | * UIMB Interrupts |
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81 | * |
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82 | * Note that the first 8 UIMB interrupts overlap the 8 external USIU |
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83 | * interrupts. |
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84 | */ |
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85 | 0, 0, 0, 0, 0, 0, 0, 0, |
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86 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
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87 | /* |
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88 | * Processor exceptions handled as interrupts |
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89 | */ |
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90 | 0 |
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91 | }; |
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92 | |
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93 | static void CPU_USIU_irq_init(void) |
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94 | { |
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95 | /* |
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96 | * In theory we should initialize two registers at least : SIMASK and |
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97 | * SIEL. SIMASK is reset at 0 value meaning no interrupts. If someone |
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98 | * find a reasonnable value for SIEL, and the need to change it, please |
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99 | * feel free to add it here. |
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100 | */ |
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101 | ppc_cached_irq_mask = 0; |
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102 | usiu.simask = ppc_cached_irq_mask; |
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103 | usiu.sipend = 0xffff0000; |
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104 | usiu.siel = usiu.siel; |
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105 | } |
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106 | |
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107 | /* |
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108 | * Initialize UIMB interrupt management |
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109 | */ |
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110 | static void CPU_UIMB_irq_init(void) |
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111 | { |
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112 | } |
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113 | |
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114 | void CPU_rtems_irq_mng_init(unsigned cpuId) |
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115 | { |
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116 | rtems_raw_except_connect_data vectorDesc; |
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117 | int i; |
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118 | |
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119 | CPU_USIU_irq_init(); |
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120 | CPU_UIMB_irq_init(); |
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121 | /* |
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122 | * Initialize Rtems management interrupt table |
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123 | */ |
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124 | /* |
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125 | * re-init the rtemsIrq table |
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126 | */ |
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127 | for (i = 0; i < CPU_IRQ_COUNT; i++) { |
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128 | rtemsIrq[i] = defaultIrq; |
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129 | rtemsIrq[i].name = i; |
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130 | } |
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131 | /* |
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132 | * Init initial Interrupt management config |
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133 | */ |
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134 | initial_config.irqNb = CPU_IRQ_COUNT; |
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135 | initial_config.defaultEntry = defaultIrq; |
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136 | initial_config.irqHdlTbl = rtemsIrq; |
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137 | initial_config.irqBase = CPU_ASM_IRQ_VECTOR_BASE; |
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138 | initial_config.irqPrioTbl = irqPrioTable; |
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139 | |
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140 | if (!CPU_rtems_irq_mngt_set(&initial_config)) { |
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141 | /* |
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142 | * put something here that will show the failure... |
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143 | */ |
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144 | rtems_panic("Unable to initialize RTEMS interrupt Management\n"); |
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145 | } |
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146 | |
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147 | /* |
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148 | * We must connect the raw irq handler for the two |
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149 | * expected interrupt sources : decrementer and external interrupts. |
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150 | */ |
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151 | vectorDesc.exceptIndex = ASM_DEC_VECTOR; |
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152 | vectorDesc.hdl.vector = ASM_DEC_VECTOR; |
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153 | vectorDesc.hdl.raw_hdl = dispatch_irq_handler; |
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154 | vectorDesc.on = nop_raw_enable; |
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155 | vectorDesc.off = nop_raw_enable; |
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156 | vectorDesc.isOn = raw_is_connected; |
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157 | if (!mpc5xx_set_exception (&vectorDesc)) { |
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158 | rtems_panic("Unable to initialize RTEMS decrementer raw exception\n"); |
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159 | } |
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160 | vectorDesc.exceptIndex = ASM_EXT_VECTOR; |
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161 | vectorDesc.hdl.vector = ASM_EXT_VECTOR; |
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162 | if (!mpc5xx_set_exception (&vectorDesc)) { |
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163 | rtems_panic("Unable to initialize RTEMS external raw exception\n"); |
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164 | } |
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165 | } |
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