[8430205] | 1 | /* |
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| 2 | * irq_asm.S |
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| 3 | * |
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[359e537] | 4 | * This file contains the assembly code for the PowerPC |
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[8430205] | 5 | * IRQ veneers for RTEMS. |
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| 6 | * |
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| 7 | * The license and distribution terms for this file may be |
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[e71a3a84] | 8 | * found in the file LICENSE in this distribution or at |
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[c499856] | 9 | * http://www.rtems.org/license/LICENSE. |
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[8430205] | 10 | * |
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| 11 | * |
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| 12 | * MPC5xx port sponsored by Defence Research and Development Canada - Suffield |
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| 13 | * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) |
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| 14 | * |
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| 15 | * Derived from libbsp/powerpc/mbx8xx/irq/irq_asm.S: |
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| 16 | * |
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| 17 | * Modified to support the MCP750. |
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| 18 | * Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr |
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| 19 | * |
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| 20 | * Till Straumann <strauman@slac.stanford.edu>, 2003/7: |
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| 21 | * - store isr nesting level in _ISR_Nest_level rather than |
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| 22 | * SPRG0 - RTEMS relies on that variable. |
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| 23 | */ |
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[359e537] | 24 | |
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[297d99b1] | 25 | #include <rtems/asm.h> |
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[8430205] | 26 | #include <rtems/score/cpu.h> |
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[5048a0a] | 27 | #include <rtems/score/percpu.h> |
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[8430205] | 28 | #include <libcpu/vectors.h> |
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| 29 | #include <libcpu/raw_exception.h> |
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[5249a4c] | 30 | #include <bsp.h> |
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[8430205] | 31 | |
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| 32 | #define SYNC \ |
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| 33 | sync; \ |
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| 34 | isync |
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[359e537] | 35 | |
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[8430205] | 36 | /* |
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| 37 | * Common handler for interrupt exceptions. |
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| 38 | * |
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| 39 | * The function CPU_rtems_irq_mng_init() initializes the decrementer and |
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| 40 | * external interrupt entries in the exception handler table with pointers |
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| 41 | * to this routine, which saves the remainder of the interrupted code's |
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| 42 | * state, then calls C_dispatch_irq_handler(). |
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| 43 | * |
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| 44 | * On entry, R1 points to a new exception stack frame in which R3, R4, and |
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| 45 | * LR have been saved. R4 holds the exception number. |
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| 46 | */ |
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| 47 | PUBLIC_VAR(C_dispatch_irq_handler) |
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[359e537] | 48 | |
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[8430205] | 49 | PUBLIC_VAR(dispatch_irq_handler) |
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| 50 | SYM (dispatch_irq_handler): |
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| 51 | /* |
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[359e537] | 52 | * Save SRR0/SRR1 As soon As possible as it is the minimal needed |
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[8430205] | 53 | * to re-enable exception processing. |
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[359e537] | 54 | * |
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[8430205] | 55 | * Note that R2 should never change (it's the EABI pointer to |
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[359e537] | 56 | * .sdata2), but we save it just in case. |
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[8430205] | 57 | */ |
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| 58 | stw r0, GPR0_OFFSET(r1) |
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| 59 | stw r2, GPR2_OFFSET(r1) |
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[359e537] | 60 | |
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[8430205] | 61 | mfsrr0 r0 |
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| 62 | mfsrr1 r3 |
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[359e537] | 63 | |
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[8430205] | 64 | stw r0, SRR0_FRAME_OFFSET(r1) |
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| 65 | stw r3, SRR1_FRAME_OFFSET(r1) |
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| 66 | |
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| 67 | /* |
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| 68 | * Enable exception recovery. Also enable FP so that FP context |
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| 69 | * can be saved and restored (using FP instructions). |
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| 70 | */ |
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| 71 | mfmsr r3 |
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| 72 | ori r3, r3, MSR_RI | MSR_FP |
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| 73 | mtmsr r3 |
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| 74 | SYNC |
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| 75 | |
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| 76 | /* |
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| 77 | * Push C scratch registers on the current stack. It may actually be |
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| 78 | * the thread stack or the interrupt stack. Anyway we have to make |
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| 79 | * it in order to be able to call C/C++ functions. Depending on the |
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| 80 | * nesting interrupt level, we will switch to the right stack later. |
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| 81 | */ |
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| 82 | stw r5, GPR5_OFFSET(r1) |
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| 83 | stw r6, GPR6_OFFSET(r1) |
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| 84 | stw r7, GPR7_OFFSET(r1) |
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| 85 | stw r8, GPR8_OFFSET(r1) |
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| 86 | stw r9, GPR9_OFFSET(r1) |
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| 87 | stw r10, GPR10_OFFSET(r1) |
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| 88 | stw r11, GPR11_OFFSET(r1) |
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| 89 | stw r12, GPR12_OFFSET(r1) |
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| 90 | stw r13, GPR13_OFFSET(r1) |
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| 91 | |
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| 92 | mfcr r5 |
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| 93 | mfctr r6 |
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| 94 | mfxer r7 |
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[359e537] | 95 | |
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[8430205] | 96 | stw r5, EXC_CR_OFFSET(r1) |
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| 97 | stw r6, EXC_CTR_OFFSET(r1) |
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| 98 | stw r7, EXC_XER_OFFSET(r1) |
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[359e537] | 99 | |
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[8430205] | 100 | /* |
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| 101 | * Add some non volatile registers to store information that will be |
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| 102 | * used when returning from C handler. |
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| 103 | */ |
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| 104 | stw r14, GPR14_OFFSET(r1) |
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| 105 | stw r15, GPR15_OFFSET(r1) |
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| 106 | |
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| 107 | /* |
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| 108 | * Save current stack pointer location in R14. |
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| 109 | */ |
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| 110 | addi r14, r1, 0 |
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| 111 | |
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| 112 | /* |
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[e626c60] | 113 | * store part of THREAD_DISPATCH_DISABLE_LEVEL address in R15 |
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[8430205] | 114 | */ |
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[e626c60] | 115 | addis r15, 0, THREAD_DISPATCH_DISABLE_LEVEL@ha |
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[8430205] | 116 | |
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| 117 | /* |
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| 118 | * Retrieve current nesting level from _ISR_Nest_level |
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| 119 | */ |
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[5048a0a] | 120 | lis r7, ISR_NEST_LEVEL@ha |
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| 121 | lwz r3, ISR_NEST_LEVEL@l(r7) |
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[8430205] | 122 | |
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| 123 | /* |
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| 124 | * Check if stack switch is necessary |
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| 125 | */ |
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| 126 | cmpwi r3, 0 |
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| 127 | bne nested |
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| 128 | |
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| 129 | mfspr r1, SPRG1 /* switch to interrupt stack */ |
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[359e537] | 130 | nested: |
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[8430205] | 131 | |
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[359e537] | 132 | /* |
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[8430205] | 133 | * Start Incrementing nesting level in R3 |
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| 134 | */ |
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| 135 | addi r3, r3, 1 |
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| 136 | |
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| 137 | /* |
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[e626c60] | 138 | * Start Incrementing THREAD_DISPATCH_DISABLE_LEVEL R4 = THREAD_DISPATCH_DISABLE_LEVEL |
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[8430205] | 139 | */ |
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[e626c60] | 140 | lwz r6, THREAD_DISPATCH_DISABLE_LEVEL@l(r15) |
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[8430205] | 141 | |
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| 142 | /* store new nesting level in _ISR_Nest_level */ |
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[5048a0a] | 143 | stw r3, ISR_NEST_LEVEL@l(r7) |
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[8430205] | 144 | |
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| 145 | addi r6, r6, 1 |
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| 146 | |
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| 147 | /* |
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[e626c60] | 148 | * store new THREAD_DISPATCH_DISABLE_LEVEL value |
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[8430205] | 149 | */ |
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[e626c60] | 150 | stw r6, THREAD_DISPATCH_DISABLE_LEVEL@l(r15) |
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[8430205] | 151 | |
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| 152 | /* |
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| 153 | * We are now running on the interrupt stack. External and decrementer |
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| 154 | * exceptions are still disabled. I see no purpose trying to optimize |
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[359e537] | 155 | * further assembler code. |
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[8430205] | 156 | */ |
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| 157 | |
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| 158 | /* |
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[359e537] | 159 | * Call C exception handler for decrementer or external interrupt. |
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[8430205] | 160 | * Pass frame along just in case.. |
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| 161 | * |
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| 162 | * C_dispatch_irq_handler(cpu_interrupt_frame* r3, vector r4) |
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| 163 | */ |
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| 164 | addi r3, r14, 0x8 |
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| 165 | bl C_dispatch_irq_handler |
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| 166 | |
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| 167 | /* |
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[359e537] | 168 | * start decrementing nesting level. Note : do not test result against 0 |
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[8430205] | 169 | * value as an easy exit condition because if interrupt nesting level > 1 |
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[e626c60] | 170 | * then THREAD_DISPATCH_DISABLE_LEVEL > 1 |
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[8430205] | 171 | */ |
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[5048a0a] | 172 | lis r7, ISR_NEST_LEVEL@ha |
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| 173 | lwz r4, ISR_NEST_LEVEL@l(r7) |
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[8430205] | 174 | |
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| 175 | /* |
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[e626c60] | 176 | * start decrementing THREAD_DISPATCH_DISABLE_LEVEL |
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[8430205] | 177 | */ |
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[e626c60] | 178 | lwz r3,THREAD_DISPATCH_DISABLE_LEVEL@l(r15) |
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[8430205] | 179 | |
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| 180 | addi r4, r4, -1 /* Continue decrementing nesting level */ |
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[e626c60] | 181 | addi r3, r3, -1 /* Continue decrementing THREAD_DISPATCH_DISABLE_LEVEL */ |
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[8430205] | 182 | |
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[5048a0a] | 183 | stw r4, ISR_NEST_LEVEL@l(r7) /* End decrementing nesting level */ |
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[e626c60] | 184 | stw r3,THREAD_DISPATCH_DISABLE_LEVEL@l(r15) /* End decrementing THREAD_DISPATCH_DISABLE_LEVEL */ |
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[8430205] | 185 | |
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| 186 | cmpwi r3, 0 |
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| 187 | |
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| 188 | /* |
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[359e537] | 189 | * switch back to original stack (done here just optimize registers |
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[8430205] | 190 | * contention. Could have been done before...) |
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| 191 | */ |
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| 192 | addi r1, r14, 0 |
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[e626c60] | 193 | bne easy_exit /* if (THREAD_DISPATCH_DISABLE_LEVEL != 0) goto easy_exit */ |
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[8430205] | 194 | |
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| 195 | /* |
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| 196 | * Here we are running again on the thread system stack. |
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[e626c60] | 197 | * We have interrupt nesting level = THREAD_DISPATCH_DISABLE_LEVEL = 0. |
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[359e537] | 198 | * Interrupt are still disabled. Time to check if scheduler request to |
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[8430205] | 199 | * do something with the current thread... |
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| 200 | */ |
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[5048a0a] | 201 | addis r4, 0, DISPATCH_NEEDED@ha |
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| 202 | lbz r5, DISPATCH_NEEDED@l(r4) |
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[8430205] | 203 | cmpwi r5, 0 |
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| 204 | beq easy_exit |
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| 205 | |
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| 206 | /* |
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[5048a0a] | 207 | * going to call _Thread_Dispatch |
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[8430205] | 208 | * Push a complete exception like frame... |
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| 209 | */ |
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| 210 | stmw r16, GPR16_OFFSET(r1) |
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| 211 | addi r3, r1, 0x8 |
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| 212 | |
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| 213 | /* |
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| 214 | * compute SP at exception entry |
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| 215 | */ |
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| 216 | addi r4, r1, EXCEPTION_FRAME_END |
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| 217 | |
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| 218 | /* |
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| 219 | * store it at the right place |
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| 220 | */ |
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| 221 | stw r4, GPR1_OFFSET(r1) |
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| 222 | |
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| 223 | /* |
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| 224 | * Call High Level signal handling code |
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| 225 | */ |
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[5048a0a] | 226 | bl _Thread_Dispatch |
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[8430205] | 227 | |
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| 228 | /* |
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| 229 | * start restoring exception like frame |
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| 230 | */ |
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| 231 | lwz r31, EXC_CTR_OFFSET(r1) |
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| 232 | lwz r30, EXC_XER_OFFSET(r1) |
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| 233 | lwz r29, EXC_CR_OFFSET(r1) |
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| 234 | lwz r28, EXC_LR_OFFSET(r1) |
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[359e537] | 235 | |
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[8430205] | 236 | mtctr r31 |
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| 237 | mtxer r30 |
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| 238 | mtcr r29 |
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| 239 | mtlr r28 |
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[359e537] | 240 | |
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[8430205] | 241 | lmw r4, GPR4_OFFSET(r1) |
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| 242 | lwz r2, GPR2_OFFSET(r1) |
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| 243 | lwz r0, GPR0_OFFSET(r1) |
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| 244 | |
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| 245 | /* |
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| 246 | * Make path non recoverable... |
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| 247 | */ |
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| 248 | mtspr nri, r0 |
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| 249 | SYNC |
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| 250 | |
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| 251 | /* |
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| 252 | * Restore rfi related settings |
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| 253 | */ |
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[359e537] | 254 | |
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[8430205] | 255 | lwz r3, SRR1_FRAME_OFFSET(r1) |
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| 256 | mtsrr1 r3 |
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| 257 | lwz r3, SRR0_FRAME_OFFSET(r1) |
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| 258 | mtsrr0 r3 |
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[359e537] | 259 | |
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[8430205] | 260 | lwz r3, GPR3_OFFSET(r1) |
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| 261 | addi r1,r1, EXCEPTION_FRAME_END |
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| 262 | SYNC |
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| 263 | rfi |
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| 264 | |
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[359e537] | 265 | |
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| 266 | easy_exit: |
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[8430205] | 267 | /* |
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| 268 | * start restoring interrupt frame |
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| 269 | */ |
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| 270 | lwz r3, EXC_CTR_OFFSET(r1) |
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| 271 | lwz r4, EXC_XER_OFFSET(r1) |
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| 272 | lwz r5, EXC_CR_OFFSET(r1) |
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| 273 | lwz r6, EXC_LR_OFFSET(r1) |
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[359e537] | 274 | |
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[8430205] | 275 | mtctr r3 |
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| 276 | mtxer r4 |
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| 277 | mtcr r5 |
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| 278 | mtlr r6 |
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| 279 | |
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| 280 | lwz r15, GPR15_OFFSET(r1) |
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| 281 | lwz r14, GPR14_OFFSET(r1) |
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| 282 | lwz r13, GPR13_OFFSET(r1) |
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| 283 | lwz r12, GPR12_OFFSET(r1) |
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| 284 | lwz r11, GPR11_OFFSET(r1) |
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| 285 | lwz r10, GPR10_OFFSET(r1) |
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| 286 | lwz r9, GPR9_OFFSET(r1) |
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| 287 | lwz r8, GPR8_OFFSET(r1) |
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| 288 | lwz r7, GPR7_OFFSET(r1) |
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| 289 | lwz r6, GPR6_OFFSET(r1) |
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| 290 | lwz r5, GPR5_OFFSET(r1) |
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| 291 | |
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| 292 | /* |
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| 293 | * Disable nested exception processing. |
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| 294 | */ |
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| 295 | mtspr nri, r0 |
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| 296 | SYNC |
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| 297 | |
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| 298 | /* |
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| 299 | * Restore rfi related settings |
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| 300 | */ |
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| 301 | lwz r4, SRR1_FRAME_OFFSET(r1) |
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| 302 | lwz r3, SRR0_FRAME_OFFSET(r1) |
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| 303 | lwz r2, GPR2_OFFSET(r1) |
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| 304 | lwz r0, GPR0_OFFSET(r1) |
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| 305 | |
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| 306 | mtsrr1 r4 |
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| 307 | mtsrr0 r3 |
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| 308 | lwz r4, GPR4_OFFSET(r1) |
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| 309 | lwz r3, GPR3_OFFSET(r1) |
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| 310 | addi r1,r1, EXCEPTION_FRAME_END |
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| 311 | SYNC |
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| 312 | rfi |
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