source: rtems/bsps/powerpc/ss555/include/bsp.h @ c991eeec

Last change on this file since c991eeec was c991eeec, checked in by Sebastian Huber <sebastian.huber@…>, on Mar 4, 2019 at 2:32:15 PM

bsps: Adjust bsp.h Doxygen groups

Update #3706.

  • Property mode set to 100644
File size: 2.6 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup RTEMSBSPsPowerPCSS555
5 *
6 * @brief Global BSP definitions.
7 */
8
9/*
10 *  This file includes definitions for the Intec SS555.
11 */
12
13/*
14 *  SS555 port sponsored by Defence Research and Development Canada - Suffield
15 *  Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
16 *
17 *  Derived from c/src/lib/libbsp/powerpc/mbx8xx/include/bsp.h:
18 *
19 *  COPYRIGHT (c) 1989-1998.
20 *  On-Line Applications Research Corporation (OAR).
21 *
22 *  The license and distribution terms for this file may be
23 *  found in the file LICENSE in this distribution or at
24 *  http://www.rtems.org/license/LICENSE.
25 */
26
27#ifndef LIBBSP_POWERPC_SS555_BSP_H
28#define LIBBSP_POWERPC_SS555_BSP_H
29
30/**
31 * @defgroup RTEMSBSPsPowerPCSS555 SS555
32 *
33 * @ingroup RTEMSBSPsPowerPC
34 *
35 * @brief SS555 Board Support Package.
36 *
37 * @{
38 */
39
40#include <bspopts.h>
41
42#ifdef ASM
43
44#define eie     0x050   /* External Interrupt Enable Register */
45#define eid     0x051   /* External Interrupt Disable Register */
46#define nri     0x052   /* Non-Recoverable Interrupt Register */
47
48#else /* !ASM */
49
50#include <bsp/default-initial-extension.h>
51
52#include <rtems.h>
53#include <mpc5xx.h>
54#include <mpc5xx/console.h>
55#include <libcpu/vectors.h>
56#include <bsp/irq.h>
57
58#ifdef __cplusplus
59extern "C" {
60#endif
61
62/*
63 * Clock definitions
64 */
65
66#define BSP_CRYSTAL_HZ   4000000        /* crystal frequency, Hz */
67#define BSP_CLOCK_HZ    40000000        /* CPU clock frequency, Hz */
68
69/*
70 * I/O definitions
71 *
72 * The SS555 board includes a CPLD to control on-board features and
73 * off-board devices.
74 */
75typedef struct cpld_ {
76  uint8_t       cs3a[32];               /* Chip select 3A */
77  uint8_t       pad0[0x200000 - 0x000020];
78
79  uint8_t       cs3b[32];               /* Chip select 3B */
80  uint8_t       pad2[0x400000 - 0x200020];
81
82  uint8_t       cs3c[32];               /* Chip select 3C */
83  uint8_t       pad4[0x600000 - 0x400020];
84
85  uint8_t       cs3d[32];               /* Chip select 3D */
86  uint8_t       pad6[0x800000 - 0x600020];
87
88  uint8_t       serial_ints;    /* Enable/disable serial interrupts */
89  uint8_t       serial_resets;  /* Enable/disable serial resets */
90  uint8_t       serial_ack;     /* Acknowledge serial transfers */
91  uint8_t       pad8[0xA00000 - 0x800003];
92
93  uint8_t       iflash_writess; /* Enable/disable internal-flash writes */
94  uint8_t       nflash_writess; /* Enable/disable NAND-flash writes */
95  uint8_t       padA[0xC00000 - 0xA00002];
96} cpld_t;
97
98extern volatile cpld_t cpld;              /* defined in linkcmds */
99
100/* clock/p_clock.c */
101extern int BSP_disconnect_clock_handler (void);
102
103extern int BSP_connect_clock_handler (rtems_irq_hdl hdl);
104
105/*
106 *  Prototypes for methods called from .S to support dependency tracking.
107 */
108void _InitSS555(void);
109
110#ifdef __cplusplus
111}
112#endif
113
114#endif /* !ASM */
115
116/** @} */
117
118#endif
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