source: rtems/bsps/powerpc/ss555/include/bsp.h @ 5249a4c

Last change on this file since 5249a4c was 5249a4c, checked in by Sebastian Huber <sebastian.huber@…>, on Jun 7, 2018 at 5:18:23 AM

powerpc: Fix ss555 build

The mpc555 define is provided via <bspopts.h>. It must not be used in
cpukit header files.

Update #3425.

  • Property mode set to 100644
File size: 2.4 KB
Line 
1/*
2 *  This file includes definitions for the Intec SS555.
3 */
4
5/*
6 *  SS555 port sponsored by Defence Research and Development Canada - Suffield
7 *  Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
8 *
9 *  Derived from c/src/lib/libbsp/powerpc/mbx8xx/include/bsp.h:
10 *
11 *  COPYRIGHT (c) 1989-1998.
12 *  On-Line Applications Research Corporation (OAR).
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.org/license/LICENSE.
17 */
18
19#ifndef LIBBSP_POWERPC_SS555_BSP_H
20#define LIBBSP_POWERPC_SS555_BSP_H
21
22#include <bspopts.h>
23
24#ifdef ASM
25
26#define eie     0x050   /* External Interrupt Enable Register */
27#define eid     0x051   /* External Interrupt Disable Register */
28#define nri     0x052   /* Non-Recoverable Interrupt Register */
29
30#else /* !ASM */
31
32#include <bsp/default-initial-extension.h>
33
34#include <rtems.h>
35#include <mpc5xx.h>
36#include <mpc5xx/console.h>
37#include <libcpu/vectors.h>
38#include <bsp/irq.h>
39
40#ifdef __cplusplus
41extern "C" {
42#endif
43
44/*
45 * Clock definitions
46 */
47
48#define BSP_CRYSTAL_HZ   4000000        /* crystal frequency, Hz */
49#define BSP_CLOCK_HZ    40000000        /* CPU clock frequency, Hz */
50
51/*
52 * I/O definitions
53 *
54 * The SS555 board includes a CPLD to control on-board features and
55 * off-board devices.
56 */
57typedef struct cpld_ {
58  uint8_t       cs3a[32];               /* Chip select 3A */
59  uint8_t       pad0[0x200000 - 0x000020];
60
61  uint8_t       cs3b[32];               /* Chip select 3B */
62  uint8_t       pad2[0x400000 - 0x200020];
63
64  uint8_t       cs3c[32];               /* Chip select 3C */
65  uint8_t       pad4[0x600000 - 0x400020];
66
67  uint8_t       cs3d[32];               /* Chip select 3D */
68  uint8_t       pad6[0x800000 - 0x600020];
69
70  uint8_t       serial_ints;    /* Enable/disable serial interrupts */
71  uint8_t       serial_resets;  /* Enable/disable serial resets */
72  uint8_t       serial_ack;     /* Acknowledge serial transfers */
73  uint8_t       pad8[0xA00000 - 0x800003];
74
75  uint8_t       iflash_writess; /* Enable/disable internal-flash writes */
76  uint8_t       nflash_writess; /* Enable/disable NAND-flash writes */
77  uint8_t       padA[0xC00000 - 0xA00002];
78} cpld_t;
79
80extern volatile cpld_t cpld;              /* defined in linkcmds */
81
82/* clock/p_clock.c */
83extern int BSP_disconnect_clock_handler (void);
84
85extern int BSP_connect_clock_handler (rtems_irq_hdl hdl);
86
87/*
88 *  Prototypes for methods called from .S to support dependency tracking.
89 */
90void _InitSS555(void);
91
92#ifdef __cplusplus
93}
94#endif
95
96#endif /* !ASM */
97
98#endif
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