[f62c7daa] | 1 | /* |
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[a800d09c] | 2 | * This file includes definitions for the Intec SS555. |
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[f62c7daa] | 3 | */ |
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| 4 | |
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| 5 | /* |
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[a800d09c] | 6 | * SS555 port sponsored by Defence Research and Development Canada - Suffield |
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| 7 | * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) |
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| 8 | * |
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| 9 | * Derived from c/src/lib/libbsp/powerpc/mbx8xx/include/bsp.h: |
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| 10 | * |
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| 11 | * COPYRIGHT (c) 1989-1998. |
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| 12 | * On-Line Applications Research Corporation (OAR). |
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| 13 | * |
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| 14 | * The license and distribution terms for this file may be |
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| 15 | * found in the file LICENSE in this distribution or at |
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[c499856] | 16 | * http://www.rtems.org/license/LICENSE. |
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[a800d09c] | 17 | */ |
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| 18 | |
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[9cff822a] | 19 | #ifndef LIBBSP_POWERPC_SS555_BSP_H |
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| 20 | #define LIBBSP_POWERPC_SS555_BSP_H |
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[a800d09c] | 21 | |
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| 22 | #include <bspopts.h> |
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[5249a4c] | 23 | |
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| 24 | #ifdef ASM |
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| 25 | |
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| 26 | #define eie 0x050 /* External Interrupt Enable Register */ |
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| 27 | #define eid 0x051 /* External Interrupt Disable Register */ |
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| 28 | #define nri 0x052 /* Non-Recoverable Interrupt Register */ |
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| 29 | |
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| 30 | #else /* !ASM */ |
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| 31 | |
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[a052181] | 32 | #include <bsp/default-initial-extension.h> |
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[a800d09c] | 33 | |
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| 34 | #include <rtems.h> |
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| 35 | #include <mpc5xx.h> |
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| 36 | #include <mpc5xx/console.h> |
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| 37 | #include <libcpu/vectors.h> |
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| 38 | #include <bsp/irq.h> |
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| 39 | |
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[46dde0fc] | 40 | #ifdef __cplusplus |
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| 41 | extern "C" { |
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| 42 | #endif |
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| 43 | |
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[a800d09c] | 44 | /* |
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| 45 | * Clock definitions |
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| 46 | */ |
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[6128a4a] | 47 | |
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[a800d09c] | 48 | #define BSP_CRYSTAL_HZ 4000000 /* crystal frequency, Hz */ |
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[5249a4c] | 49 | #define BSP_CLOCK_HZ 40000000 /* CPU clock frequency, Hz */ |
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[a800d09c] | 50 | |
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| 51 | /* |
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| 52 | * I/O definitions |
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| 53 | * |
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| 54 | * The SS555 board includes a CPLD to control on-board features and |
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| 55 | * off-board devices. |
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| 56 | */ |
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| 57 | typedef struct cpld_ { |
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[76f9c44] | 58 | uint8_t cs3a[32]; /* Chip select 3A */ |
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| 59 | uint8_t pad0[0x200000 - 0x000020]; |
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[a800d09c] | 60 | |
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[76f9c44] | 61 | uint8_t cs3b[32]; /* Chip select 3B */ |
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| 62 | uint8_t pad2[0x400000 - 0x200020]; |
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[a800d09c] | 63 | |
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[76f9c44] | 64 | uint8_t cs3c[32]; /* Chip select 3C */ |
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| 65 | uint8_t pad4[0x600000 - 0x400020]; |
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[a800d09c] | 66 | |
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[76f9c44] | 67 | uint8_t cs3d[32]; /* Chip select 3D */ |
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| 68 | uint8_t pad6[0x800000 - 0x600020]; |
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[a800d09c] | 69 | |
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[76f9c44] | 70 | uint8_t serial_ints; /* Enable/disable serial interrupts */ |
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| 71 | uint8_t serial_resets; /* Enable/disable serial resets */ |
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| 72 | uint8_t serial_ack; /* Acknowledge serial transfers */ |
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| 73 | uint8_t pad8[0xA00000 - 0x800003]; |
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[a800d09c] | 74 | |
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[76f9c44] | 75 | uint8_t iflash_writess; /* Enable/disable internal-flash writes */ |
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| 76 | uint8_t nflash_writess; /* Enable/disable NAND-flash writes */ |
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| 77 | uint8_t padA[0xC00000 - 0xA00002]; |
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[a800d09c] | 78 | } cpld_t; |
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[6128a4a] | 79 | |
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[a800d09c] | 80 | extern volatile cpld_t cpld; /* defined in linkcmds */ |
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[6128a4a] | 81 | |
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[8502b16] | 82 | /* clock/p_clock.c */ |
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| 83 | extern int BSP_disconnect_clock_handler (void); |
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| 84 | |
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| 85 | extern int BSP_connect_clock_handler (rtems_irq_hdl hdl); |
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| 86 | |
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[f62c7daa] | 87 | /* |
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| 88 | * Prototypes for methods called from .S to support dependency tracking. |
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| 89 | */ |
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| 90 | void _InitSS555(void); |
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| 91 | |
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[a800d09c] | 92 | #ifdef __cplusplus |
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| 93 | } |
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| 94 | #endif |
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| 95 | |
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[f62c7daa] | 96 | #endif /* !ASM */ |
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| 97 | |
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[a800d09c] | 98 | #endif |
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