source: rtems/bsps/powerpc/shared/start/bsp-start-zero.S @ 81aec18

5
Last change on this file since 81aec18 was 81aec18, checked in by Sebastian Huber <sebastian.huber@…>, on 01/24/19 at 13:29:03

bsps/powerpc: Fix 64-bit issues in assembler files

We have to be careful with instructions which operate explicitly on
words or doublewords.

Update #3082.

  • Property mode set to 100644
File size: 2.1 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup bsp_start
5 *
6 * @brief bsp_start_zero() implementation.
7 */
8
9/*
10 * Copyright (c) 2010-2014 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Dornierstr. 4
14 *  82178 Puchheim
15 *  Germany
16 *  <rtems@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.org/license/LICENSE.
21 */
22
23#include <rtems/asm.h>
24#include <libcpu/powerpc-utility.h>
25#include <bspopts.h>
26
27        .globl bsp_start_zero
28        .globl bsp_start_zero_begin
29        .globl bsp_start_zero_end
30        .globl bsp_start_zero_size
31
32        .section ".bsp_start_text", "ax"
33        .type bsp_start_zero, @function
34bsp_start_zero:
35bsp_start_zero_begin:
36        li      r0, 0
37        subi    r11, r3, 1
38        CLEAR_RIGHT_IMMEDIATE   r11, r11, PPC_CACHE_ALIGN_POWER
39        addi    r10, r11, PPC_CACHE_ALIGNMENT
40        subf    r11, r3, r10
41        COMPARE_LOGICAL cr7, r11, r4
42        add     r9, r3, r4
43        ble-    cr7, head_end_done
44        mr      r10, r9
45head_end_done:
46        subf    r11, r3, r10
47        addi    r11, r11, 1
48        mtctr   r11
49
50        /* Head loop */
51        b       head_loop_update
52head_loop_begin:
53        stb     r0, 0(r3)
54        addi    r3, r3, 1
55head_loop_update:
56        bdnz+   head_loop_begin
57
58        subf    r11, r3, r9
59        SHIFT_RIGHT_IMMEDIATE   r11, r11, PPC_CACHE_ALIGN_POWER
60        addi    r11, r11, 1
61        mtctr   r11
62
63        /* Main loop */
64        b       main_loop_update
65main_loop_begin:
66#if BSP_DATA_CACHE_ENABLED
67        dcbz    r0, r3
68        dcbf    r0, r3
69#else
70  #if PPC_CACHE_ALIGNMENT == 32 || PPC_CACHE_ALIGNMENT == 64
71        stw     r0, 0(r3)
72        stw     r0, 4(r3)
73        stw     r0, 8(r3)
74        stw     r0, 12(r3)
75        stw     r0, 16(r3)
76        stw     r0, 20(r3)
77        stw     r0, 24(r3)
78        stw     r0, 28(r3)
79    #if PPC_CACHE_ALIGNMENT == 64
80        stw     r0, 32(r3)
81        stw     r0, 36(r3)
82        stw     r0, 40(r3)
83        stw     r0, 44(r3)
84        stw     r0, 48(r3)
85        stw     r0, 52(r3)
86        stw     r0, 56(r3)
87        stw     r0, 60(r3)
88    #endif
89  #else
90    #error "unsupported cache alignment"
91  #endif
92#endif
93        addi    r3, r3, PPC_CACHE_ALIGNMENT
94main_loop_update:
95        bdnz+   main_loop_begin
96
97        subf    r9, r3, r9
98        addi    r9, r9, 1
99        mtctr   r9
100
101        /* Tail loop */
102        b       tail_loop_update
103tail_loop_begin:
104        stb     r0, 0(r3)
105        addi    r3, r3, 1
106tail_loop_update:
107        bdnz+   tail_loop_begin
108
109        /* Return */
110        sync
111        isync
112        blr
113
114bsp_start_zero_end:
115        .set bsp_start_zero_size, bsp_start_zero_end - bsp_start_zero_begin
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