1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup bsp_start |
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5 | * |
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6 | * @brief bsp_start_zero() implementation. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2010-2014 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Dornierstr. 4 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <rtems@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.org/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #include <rtems/asm.h> |
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24 | #include <libcpu/powerpc-utility.h> |
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25 | #include <bspopts.h> |
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26 | |
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27 | .globl bsp_start_zero |
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28 | .globl bsp_start_zero_begin |
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29 | .globl bsp_start_zero_end |
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30 | .globl bsp_start_zero_size |
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31 | |
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32 | .section ".bsp_start_text", "ax" |
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33 | .type bsp_start_zero, @function |
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34 | bsp_start_zero: |
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35 | bsp_start_zero_begin: |
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36 | li r0, 0 |
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37 | subi r11, r3, 1 |
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38 | CLEAR_RIGHT_IMMEDIATE r11, r11, PPC_CACHE_ALIGN_POWER |
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39 | addi r10, r11, PPC_CACHE_ALIGNMENT |
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40 | subf r11, r3, r10 |
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41 | COMPARE_LOGICAL cr7, r11, r4 |
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42 | add r9, r3, r4 |
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43 | ble- cr7, head_end_done |
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44 | mr r10, r9 |
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45 | head_end_done: |
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46 | subf r11, r3, r10 |
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47 | addi r11, r11, 1 |
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48 | mtctr r11 |
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49 | |
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50 | /* Head loop */ |
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51 | b head_loop_update |
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52 | head_loop_begin: |
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53 | stb r0, 0(r3) |
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54 | addi r3, r3, 1 |
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55 | head_loop_update: |
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56 | bdnz+ head_loop_begin |
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57 | |
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58 | subf r11, r3, r9 |
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59 | SHIFT_RIGHT_IMMEDIATE r11, r11, PPC_CACHE_ALIGN_POWER |
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60 | addi r11, r11, 1 |
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61 | mtctr r11 |
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62 | |
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63 | /* Main loop */ |
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64 | b main_loop_update |
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65 | main_loop_begin: |
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66 | #if BSP_DATA_CACHE_ENABLED |
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67 | dcbz r0, r3 |
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68 | dcbf r0, r3 |
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69 | #else |
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70 | #if PPC_CACHE_ALIGNMENT == 32 || PPC_CACHE_ALIGNMENT == 64 |
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71 | stw r0, 0(r3) |
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72 | stw r0, 4(r3) |
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73 | stw r0, 8(r3) |
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74 | stw r0, 12(r3) |
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75 | stw r0, 16(r3) |
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76 | stw r0, 20(r3) |
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77 | stw r0, 24(r3) |
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78 | stw r0, 28(r3) |
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79 | #if PPC_CACHE_ALIGNMENT == 64 |
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80 | stw r0, 32(r3) |
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81 | stw r0, 36(r3) |
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82 | stw r0, 40(r3) |
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83 | stw r0, 44(r3) |
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84 | stw r0, 48(r3) |
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85 | stw r0, 52(r3) |
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86 | stw r0, 56(r3) |
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87 | stw r0, 60(r3) |
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88 | #endif |
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89 | #else |
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90 | #error "unsupported cache alignment" |
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91 | #endif |
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92 | #endif |
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93 | addi r3, r3, PPC_CACHE_ALIGNMENT |
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94 | main_loop_update: |
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95 | bdnz+ main_loop_begin |
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96 | |
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97 | subf r9, r3, r9 |
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98 | addi r9, r9, 1 |
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99 | mtctr r9 |
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100 | |
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101 | /* Tail loop */ |
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102 | b tail_loop_update |
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103 | tail_loop_begin: |
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104 | stb r0, 0(r3) |
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105 | addi r3, r3, 1 |
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106 | tail_loop_update: |
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107 | bdnz+ tail_loop_begin |
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108 | |
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109 | /* Return */ |
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110 | sync |
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111 | isync |
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112 | blr |
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113 | |
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114 | bsp_start_zero_end: |
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115 | .set bsp_start_zero_size, bsp_start_zero_end - bsp_start_zero_begin |
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