source: rtems/bsps/powerpc/shared/exceptions/ppc_exc_naked.S @ e560ee85

Last change on this file since e560ee85 was e560ee85, checked in by Joel Sherrill <joel@…>, on 03/01/22 at 21:38:55

bsps/powerpc/: Scripted embedded brains header file clean up

Updates #4625.
  • Property mode set to 100644
File size: 4.9 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup ppc_exc
5 *
6 * @brief PowerPC Exceptions implementation.
7 */
8
9/*
10 * Copyright (c) 2009 embedded brains GmbH.  All rights reserved.
11 *
12 * The license and distribution terms for this file may be
13 * found in the file LICENSE in this distribution or at
14 * http://www.rtems.org/license/LICENSE.
15 */
16
17#include "ppc_exc_asm_macros.h"
18
19        .global ppc_exc_min_prolog_tmpl_naked
20
21ppc_exc_min_prolog_tmpl_naked:
22
23        stwu    r1, -EXCEPTION_FRAME_END(r1)
24        stw     VECTOR_REGISTER, VECTOR_OFFSET(r1)
25        li      VECTOR_REGISTER, 0
26
27        /*
28         * We store the absolute branch target address here.  It will be used
29         * to generate the branch operation in ppc_exc_make_prologue().
30         */
31        .int    ppc_exc_wrap_naked
32
33        .global ppc_exc_wrap_naked
34ppc_exc_wrap_naked:
35
36        /* Save scratch registers */
37        stw     SCRATCH_REGISTER_0, SCRATCH_REGISTER_0_OFFSET(r1)
38        stw     SCRATCH_REGISTER_1, SCRATCH_REGISTER_1_OFFSET(r1)
39        stw     SCRATCH_REGISTER_2, SCRATCH_REGISTER_2_OFFSET(r1)
40
41        /* Save volatile registers */
42        stw     r0, GPR0_OFFSET(r1)
43        stw     r3, GPR3_OFFSET(r1)
44        stw     r8, GPR8_OFFSET(r1)
45        stw     r9, GPR9_OFFSET(r1)
46        stw     r10, GPR10_OFFSET(r1)
47        stw     r11, GPR11_OFFSET(r1)
48        stw     r12, GPR12_OFFSET(r1)
49
50        /* Save CR */
51        mfcr    SCRATCH_REGISTER_0
52        stw     SCRATCH_REGISTER_0, EXC_CR_OFFSET(r1)
53
54        /* Save SRR0 */
55        mfspr   SCRATCH_REGISTER_0, srr0
56        stw     SCRATCH_REGISTER_0, SRR0_FRAME_OFFSET(r1)
57
58        /* Save SRR1 */
59        mfspr   SCRATCH_REGISTER_0, srr1
60        stw     SCRATCH_REGISTER_0, SRR1_FRAME_OFFSET(r1)
61
62        /* Save CTR */
63        mfctr   SCRATCH_REGISTER_0
64        stw     SCRATCH_REGISTER_0, EXC_CTR_OFFSET(r1)
65
66        /* Save XER */
67        mfxer   SCRATCH_REGISTER_0
68        stw     SCRATCH_REGISTER_0, EXC_XER_OFFSET(r1)
69
70        /* Save LR */
71        mflr    SCRATCH_REGISTER_0
72        stw     SCRATCH_REGISTER_0, EXC_LR_OFFSET(r1)
73
74#ifndef PPC_EXC_CONFIG_BOOKE_ONLY
75
76        /* Load MSR bit mask */
77        lwz     SCRATCH_REGISTER_0, ppc_exc_msr_bits@sdarel(r13)
78
79        /*
80         * Change the MSR if necessary (MMU, RI), remember decision in
81         * non-volatile CR_MSR.
82         */
83        cmpwi   CR_MSR, SCRATCH_REGISTER_0, 0
84        bne     CR_MSR, wrap_change_msr_naked
85
86wrap_change_msr_done_naked:
87
88#endif /* PPC_EXC_CONFIG_BOOKE_ONLY */
89
90        /*
91         * Call high level exception handler
92         */
93
94        /*
95         * Get the handler table index from the vector number.  We have to
96         * discard the exception type.  Take only the least significant five
97         * bits (= LAST_VALID_EXC + 1) from the vector register.  Multiply by
98         * four (= size of function pointer).
99         */
100        rlwinm  SCRATCH_REGISTER_1, VECTOR_REGISTER, 2, 25, 29
101
102        /* Load handler table address */
103        LA      SCRATCH_REGISTER_0, ppc_exc_handler_table
104
105        /* Load handler address */
106        lwzx    SCRATCH_REGISTER_0, SCRATCH_REGISTER_0, SCRATCH_REGISTER_1
107
108        /*
109         * First parameter = exception frame pointer + FRAME_LINK_SPACE
110         *
111         * We add FRAME_LINK_SPACE to the frame pointer because the high level
112         * handler expects a BSP_Exception_frame structure.
113         */
114        addi    r3, r1, FRAME_LINK_SPACE
115
116        /*
117         * Second parameter = vector number (r4 is the VECTOR_REGISTER)
118         *
119         * Discard the exception type and store the vector number
120         * in the vector register.  Take only the least significant
121         * five bits (= LAST_VALID_EXC + 1).
122         */
123        rlwinm  VECTOR_REGISTER, VECTOR_REGISTER, 0, 27, 31
124
125        /* Call handler */
126        mtctr   SCRATCH_REGISTER_0
127        bctrl
128
129#ifndef PPC_EXC_CONFIG_BOOKE_ONLY
130
131        /* Restore MSR? */
132        bne     CR_MSR, wrap_restore_msr_naked
133
134wrap_restore_msr_done_naked:
135
136#endif /* PPC_EXC_CONFIG_BOOKE_ONLY */
137
138        /* Restore XER and CTR */
139        lwz     SCRATCH_REGISTER_0, EXC_XER_OFFSET(r1)
140        lwz     SCRATCH_REGISTER_1, EXC_CTR_OFFSET(r1)
141        mtxer   SCRATCH_REGISTER_0
142        mtctr   SCRATCH_REGISTER_1
143
144        /* Restore CR and LR */
145        lwz     SCRATCH_REGISTER_0, EXC_CR_OFFSET(r1)
146        lwz     SCRATCH_REGISTER_1, EXC_LR_OFFSET(r1)
147        mtcr    SCRATCH_REGISTER_0
148        mtlr    SCRATCH_REGISTER_1
149
150        /* Restore volatile registers */
151        lwz     r0, GPR0_OFFSET(r1)
152        lwz     r3, GPR3_OFFSET(r1)
153        lwz     r8, GPR8_OFFSET(r1)
154        lwz     r9, GPR9_OFFSET(r1)
155        lwz     r10, GPR10_OFFSET(r1)
156        lwz     r11, GPR11_OFFSET(r1)
157        lwz     r12, GPR12_OFFSET(r1)
158
159        /* Restore vector register */
160        lwz     VECTOR_REGISTER, VECTOR_OFFSET(r1)
161
162        /* Restore scratch registers and SRRs */
163        lwz     SCRATCH_REGISTER_0, SRR0_FRAME_OFFSET(r1)
164        lwz     SCRATCH_REGISTER_1, SRR1_FRAME_OFFSET(r1)
165        lwz     SCRATCH_REGISTER_2, SCRATCH_REGISTER_2_OFFSET(r1)
166        mtspr   srr0, SCRATCH_REGISTER_0
167        lwz     SCRATCH_REGISTER_0, SCRATCH_REGISTER_0_OFFSET(r1)
168        mtspr   srr1, SCRATCH_REGISTER_1
169        lwz     SCRATCH_REGISTER_1, SCRATCH_REGISTER_1_OFFSET(r1)
170
171        /*
172         * We restore r1 from the frame rather than just popping (adding to
173         * current r1) since the exception handler might have done strange
174         * things (e.g. a debugger moving and relocating the stack).
175         */
176        lwz     r1, 0(r1)
177
178        /* Return */
179        rfi
180
181#ifndef PPC_EXC_CONFIG_BOOKE_ONLY
182
183wrap_change_msr_naked:
184
185        mfmsr   SCRATCH_REGISTER_1
186        or      SCRATCH_REGISTER_1, SCRATCH_REGISTER_1, SCRATCH_REGISTER_0
187        mtmsr   SCRATCH_REGISTER_1
188        sync
189        isync
190        b       wrap_change_msr_done_naked
191
192wrap_restore_msr_naked:
193
194        lwz     SCRATCH_REGISTER_0, ppc_exc_msr_bits@sdarel(r13)
195        mfmsr   SCRATCH_REGISTER_1
196        andc    SCRATCH_REGISTER_1, SCRATCH_REGISTER_1, SCRATCH_REGISTER_0
197        mtmsr   SCRATCH_REGISTER_1
198        sync
199        isync
200        b       wrap_restore_msr_done_naked
201
202#endif /* PPC_EXC_CONFIG_BOOKE_ONLY */
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