[16a8616] | 1 | /** |
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| 2 | * @file |
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[3235ad9] | 3 | * |
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| 4 | * This routine initializes the interval timer on the |
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[16a8616] | 5 | * PowerPC 403 CPU. The tick frequency is specified by the BSP. |
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| 6 | */ |
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| 7 | |
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| 8 | /* |
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| 9 | * Original PPC403 Code from: |
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[e57b0e2] | 10 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
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[3235ad9] | 11 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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| 12 | * |
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[16a8616] | 13 | * Modifications for PPC405GP by Dennis Ehlin |
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| 14 | * |
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[3235ad9] | 15 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 16 | * without any express or implied warranty: |
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| 17 | * permission to use, copy, modify, and distribute this file |
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| 18 | * for any purpose is hereby granted without fee, provided that |
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| 19 | * the above copyright notice and this notice appears in all |
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| 20 | * copies, and that the name of i-cubed limited not be used in |
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| 21 | * advertising or publicity pertaining to distribution of the |
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| 22 | * software without specific, written prior permission. |
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| 23 | * i-cubed limited makes no representations about the suitability |
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| 24 | * of this software for any purpose. |
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| 25 | * |
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[aecfa2b] | 26 | * Modifications for deriving timer clock from cpu system clock by |
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| 27 | * Thomas Doerfler <td@imd.m.isar.de> |
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| 28 | * for these modifications: |
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| 29 | * COPYRIGHT (c) 1997 by IMD, Puchheim, Germany. |
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| 30 | * |
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[16a8616] | 31 | * COPYRIGHT (c) 1989-2012. |
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[3235ad9] | 32 | * On-Line Applications Research Corporation (OAR). |
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| 33 | * |
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[98e4ebf5] | 34 | * The license and distribution terms for this file may be |
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| 35 | * found in the file LICENSE in this distribution or at |
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[c499856] | 36 | * http://www.rtems.org/license/LICENSE. |
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[3235ad9] | 37 | */ |
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| 38 | |
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[f817b02] | 39 | #include <rtems.h> |
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[11c2382] | 40 | #include <rtems/clockdrv.h> |
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[3a4ae6c] | 41 | #include <rtems/libio.h> |
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[3235ad9] | 42 | #include <stdlib.h> /* for atexit() */ |
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[73cdeb6] | 43 | #include <rtems/bspIo.h> |
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[e1df032] | 44 | #include <rtems/powerpc/powerpc.h> |
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[b7d1f290] | 45 | |
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[73cdeb6] | 46 | /* |
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| 47 | * check, which exception handling code is present |
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| 48 | */ |
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[b7d1f290] | 49 | |
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| 50 | #include <bsp.h> |
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| 51 | |
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| 52 | #include <bsp/vectors.h> |
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[73cdeb6] | 53 | #include <bsp/irq.h> |
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[fbd06a09] | 54 | |
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[84b19b5] | 55 | extern uint32_t bsp_clicks_per_usec; |
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[3235ad9] | 56 | |
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[84b19b5] | 57 | volatile uint32_t Clock_driver_ticks; |
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[66c373bf] | 58 | static uint32_t pit_value, tick_time; |
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[84b19b5] | 59 | static bool auto_restart; |
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[3235ad9] | 60 | |
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[a6b2080] | 61 | static void Clock_exit( void ); |
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[359e537] | 62 | |
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[84b19b5] | 63 | static inline uint32_t get_itimer(void) |
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[3235ad9] | 64 | { |
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[84b19b5] | 65 | register uint32_t rc; |
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[3235ad9] | 66 | |
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[e9ae97fb] | 67 | #ifndef ppc405 /* this is a ppc403 */ |
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[16a8616] | 68 | __asm__ volatile ("mfspr %0, 0x3dd" : "=r" ((rc))); /* TBLO */ |
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[e9ae97fb] | 69 | #else /* ppc405 */ |
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[16a8616] | 70 | __asm__ volatile ("mfspr %0, 0x10c" : "=r" ((rc))); /* 405GP TBL */ |
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[e9ae97fb] | 71 | #endif /* ppc405 */ |
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[3235ad9] | 72 | |
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[16a8616] | 73 | return rc; |
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[3a4ae6c] | 74 | } |
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| 75 | |
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| 76 | /* |
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| 77 | * ISR Handler |
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| 78 | */ |
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[84b19b5] | 79 | static void Clock_isr(void* handle) |
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[3235ad9] | 80 | { |
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[84b19b5] | 81 | uint32_t clicks_til_next_interrupt; |
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[b7d1f290] | 82 | #if defined(BSP_PPC403_CLOCK_ISR_IRQ_LEVEL) |
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[84b19b5] | 83 | uint32_t l_orig = _ISR_Get_level(); |
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[16a8616] | 84 | #endif |
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| 85 | |
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| 86 | if (!auto_restart) { |
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[84b19b5] | 87 | uint32_t itimer_value; |
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[16a8616] | 88 | /* |
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| 89 | * setup for next interrupt; making sure the new value is reasonably |
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| 90 | * in the future.... in case we lost out on an interrupt somehow |
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| 91 | */ |
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| 92 | itimer_value = get_itimer(); |
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| 93 | tick_time += pit_value; |
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| 94 | |
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| 95 | /* |
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| 96 | * how far away is next interrupt *really* |
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| 97 | * It may be a long time; this subtraction works even if |
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| 98 | * Clock_clicks_interrupt < Clock_clicks_low_order via |
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| 99 | * the miracle of unsigned math. |
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| 100 | */ |
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| 101 | clicks_til_next_interrupt = tick_time - itimer_value; |
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| 102 | |
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| 103 | /* |
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| 104 | * If it is too soon then bump it up. |
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| 105 | * This should only happen if CPU_HPPA_CLICKS_PER_TICK is too small. |
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| 106 | * But setting it low is useful for debug, so... |
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| 107 | */ |
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| 108 | if (clicks_til_next_interrupt < 400) { |
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| 109 | tick_time = itimer_value + 1000; |
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| 110 | clicks_til_next_interrupt = 1000; |
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| 111 | /* XXX: count these! this should be rare */ |
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| 112 | } |
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| 113 | |
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| 114 | /* |
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| 115 | * If it is too late, that means we missed the interrupt somehow. |
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| 116 | * Rather than wait 35-50s for a wrap, we just fudge it here. |
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| 117 | */ |
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| 118 | if (clicks_til_next_interrupt > pit_value) { |
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| 119 | tick_time = itimer_value + 1000; |
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| 120 | clicks_til_next_interrupt = 1000; |
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| 121 | /* XXX: count these! this should never happen :-) */ |
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| 122 | } |
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| 123 | |
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| 124 | __asm__ volatile ("mtspr 0x3db, %0" :: "r" |
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[84b19b5] | 125 | (clicks_til_next_interrupt)); /* PIT */ |
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[e57b0e2] | 126 | } |
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[359e537] | 127 | |
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[84b19b5] | 128 | __asm__ volatile ("mtspr 0x3d8, %0" :: "r" (0x08000000)); /* TSR */ |
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[359e537] | 129 | |
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[16a8616] | 130 | Clock_driver_ticks++; |
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[359e537] | 131 | |
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[16a8616] | 132 | /* Give BSP a chance to say if they want to re-enable interrupts */ |
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[b7d1f290] | 133 | #if defined(BSP_PPC403_CLOCK_ISR_IRQ_LEVEL) |
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[16a8616] | 134 | _ISR_Set_level(BSP_PPC403_CLOCK_ISR_IRQ_LEVEL); |
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[b7d1f290] | 135 | #endif |
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[16a8616] | 136 | rtems_clock_tick(); |
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[b7d1f290] | 137 | |
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| 138 | #if defined(BSP_PPC403_CLOCK_ISR_IRQ_LEVEL) |
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[16a8616] | 139 | _ISR_Set_level(l_orig) |
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[b7d1f290] | 140 | #endif |
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[3235ad9] | 141 | } |
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| 142 | |
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[84b19b5] | 143 | static int ClockIsOn(const rtems_irq_connect_data* unused) |
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[73cdeb6] | 144 | { |
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[84b19b5] | 145 | register uint32_t tcr; |
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[359e537] | 146 | |
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[84b19b5] | 147 | __asm__ volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */ |
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[359e537] | 148 | |
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[16a8616] | 149 | return (tcr & 0x04000000) != 0; |
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[73cdeb6] | 150 | } |
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| 151 | |
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[84b19b5] | 152 | static void ClockOff(const rtems_irq_connect_data* unused) |
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[73cdeb6] | 153 | { |
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[84b19b5] | 154 | register uint32_t tcr; |
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[16a8616] | 155 | |
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[84b19b5] | 156 | __asm__ volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */ |
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[16a8616] | 157 | tcr &= ~ 0x04400000; |
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| 158 | __asm__ volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */ |
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[73cdeb6] | 159 | } |
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| 160 | |
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[84b19b5] | 161 | static void ClockOn(const rtems_irq_connect_data* unused) |
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[3235ad9] | 162 | { |
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[84b19b5] | 163 | uint32_t iocr; |
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| 164 | register uint32_t tcr; |
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| 165 | #ifndef ppc405 |
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| 166 | uint32_t pvr; |
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[e9ae97fb] | 167 | #endif /* ppc403 */ |
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[359e537] | 168 | |
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[16a8616] | 169 | Clock_driver_ticks = 0; |
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[359e537] | 170 | |
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[84b19b5] | 171 | #ifndef ppc405 /* this is a ppc403 */ |
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| 172 | __asm__ volatile ("mfdcr %0, 0xa0" : "=r" (iocr)); /* IOCR */ |
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[f3a51d62] | 173 | iocr &= ~4; /* timer clocked from system clock */ |
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[16a8616] | 174 | __asm__ volatile ("mtdcr 0xa0, %0" : "=r" (iocr) : "0" (iocr)); /* IOCR */ |
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[359e537] | 175 | |
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[16a8616] | 176 | __asm__ volatile ("mfspr %0, 0x11f" : "=r" ((pvr))); /* PVR */ |
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| 177 | if (((pvr & 0xffff0000) >> 16) != 0x0020) |
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[84b19b5] | 178 | return; /* Not a ppc403 */ |
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[359e537] | 179 | |
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[84b19b5] | 180 | if ((pvr & 0xff00) == 0x0000) /* 403GA */ |
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[aecfa2b] | 181 | #if 0 /* FIXME: in which processor versions will "autoload" work properly? */ |
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[84b19b5] | 182 | auto_restart = (pvr & 0x00f0) > 0x0000 ? true : false; |
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[359e537] | 183 | #else |
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[84b19b5] | 184 | /* no known chip version supports auto restart of timer... */ |
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| 185 | auto_restart = false; |
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[aecfa2b] | 186 | #endif |
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[84b19b5] | 187 | else if ((pvr & 0xff00) == 0x0100) /* 403GB */ |
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| 188 | auto_restart = true; |
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[16a8616] | 189 | |
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[84b19b5] | 190 | #else /* ppc405 */ |
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| 191 | __asm__ volatile ("mfdcr %0, 0x0b2" : "=r" (iocr)); /*405GP CPC0_CR1 */ |
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[f3a51d62] | 192 | iocr &=~0x800000; /* timer clocked from system clock CETE*/ |
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[84b19b5] | 193 | __asm__ volatile ("mtdcr 0x0b2, %0" : "=r" (iocr) : "0" (iocr)); /* 405GP CPC0_CR1 */ |
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[73cdeb6] | 194 | |
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[16a8616] | 195 | /* |
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| 196 | * Enable auto restart |
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| 197 | */ |
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| 198 | auto_restart = true; |
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[84b19b5] | 199 | #endif /* ppc405 */ |
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| 200 | |
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[16a8616] | 201 | pit_value = rtems_configuration_get_microseconds_per_tick() * |
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| 202 | bsp_clicks_per_usec; |
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| 203 | |
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| 204 | /* |
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| 205 | * Set PIT value |
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| 206 | */ |
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| 207 | __asm__ volatile ("mtspr 0x3db, %0" : : "r" (pit_value)); /* PIT */ |
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[0dd1d44] | 208 | |
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[84b19b5] | 209 | /* |
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| 210 | * Set timer to autoreload, bit TCR->ARE = 1 0x0400000 |
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| 211 | * Enable PIT interrupt, bit TCR->PIE = 1 0x4000000 |
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| 212 | */ |
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[16a8616] | 213 | tick_time = get_itimer() + pit_value; |
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| 214 | |
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[84b19b5] | 215 | __asm__ volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */ |
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[16a8616] | 216 | tcr = (tcr & ~0x04400000) | (auto_restart ? 0x04400000 : 0x04000000); |
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[84b19b5] | 217 | #if 1 |
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[16a8616] | 218 | __asm__ volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */ |
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| 219 | #endif |
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[3235ad9] | 220 | } |
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| 221 | |
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[5039d92] | 222 | static void Install_clock(void (*clock_isr)(void *)) |
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[3235ad9] | 223 | { |
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[16a8616] | 224 | rtems_irq_connect_data clockIrqConnData; |
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[fbd06a09] | 225 | |
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[16a8616] | 226 | Clock_driver_ticks = 0; |
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[359e537] | 227 | |
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[16a8616] | 228 | /* |
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| 229 | * initialize the interval here |
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| 230 | * First tick is set to right amount of time in the future |
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| 231 | * Future ticks will be incremented over last value set |
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| 232 | * in order to provide consistent clicks in the face of |
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| 233 | * interrupt overhead |
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| 234 | */ |
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| 235 | clockIrqConnData.on = ClockOn; |
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| 236 | clockIrqConnData.off = ClockOff; |
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| 237 | clockIrqConnData.isOn = ClockIsOn; |
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| 238 | clockIrqConnData.name = BSP_PIT; |
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| 239 | clockIrqConnData.hdl = clock_isr; |
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| 240 | if (!BSP_install_rtems_irq_handler (&clockIrqConnData)) { |
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| 241 | printk("Unable to connect Clock Irq handler\n"); |
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| 242 | rtems_fatal_error_occurred(1); |
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| 243 | } |
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[73cdeb6] | 244 | |
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[16a8616] | 245 | atexit(Clock_exit); |
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[73cdeb6] | 246 | } |
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[3235ad9] | 247 | |
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| 248 | /* |
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| 249 | * Called via atexit() |
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| 250 | * Remove the clock interrupt handler by setting handler to NULL |
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[e9ae97fb] | 251 | * |
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[359e537] | 252 | * This will not work on the 405GP because |
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| 253 | * when bit's are set in TCR they can only be unset by a reset |
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[3235ad9] | 254 | */ |
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[73cdeb6] | 255 | void Clock_exit(void) |
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[3235ad9] | 256 | { |
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[fbd06a09] | 257 | rtems_irq_connect_data clockIrqConnData; |
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[359e537] | 258 | |
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[fbd06a09] | 259 | clockIrqConnData.name = BSP_PIT; |
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| 260 | if (!BSP_get_current_rtems_irq_handler(&clockIrqConnData)) { |
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| 261 | printk("Unable to stop system clock\n"); |
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| 262 | rtems_fatal_error_occurred(1); |
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| 263 | } |
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[359e537] | 264 | |
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[fbd06a09] | 265 | BSP_remove_rtems_irq_handler (&clockIrqConnData); |
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[3235ad9] | 266 | } |
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| 267 | |
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[bb99cd0d] | 268 | void _Clock_Initialize( void ) |
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[3a4ae6c] | 269 | { |
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| 270 | Install_clock( Clock_isr ); |
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| 271 | } |
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