source: rtems/bsps/powerpc/shared/cache/cache.c @ 9964895

5
Last change on this file since 9964895 was 4cf93658, checked in by Sebastian Huber <sebastian.huber@…>, on 01/27/18 at 13:37:51

bsps: Rework cache manager implementation

The previous cache manager support used a single souce file
(cache_manager.c) which included an implementation header (cache_.h).
This required the use of specialized include paths to find the right
header file. Change this to include a generic implementation header
(cacheimpl.h) in specialized source files.

Use the following directories and files:

  • bsps/shared/cache
  • bsps/@RTEMS_CPU@/shared/cache
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILY/start/cache.c

Update #3285.

  • Property mode set to 100644
File size: 6.8 KB
Line 
1/**
2 * @file
3 *
4 * #ingroup powerpc_shared
5 *
6 * @brief Header file for the Cache Manager PowerPC support.
7 */
8
9/*
10 *  Cache Management Support Routines for the MC68040
11 * Modified for MPC8260 Andy Dachs <a.dachs@sstl.co.uk>
12 * Surrey Satellite Technology Limited (SSTL), 2001
13 */
14
15#include <rtems.h>
16#include <rtems/powerpc/powerpc.h>
17#include <rtems/powerpc/registers.h>
18
19/* Provide the CPU defines only if we have a cache */
20#if PPC_CACHE_ALIGNMENT != PPC_NO_CACHE_ALIGNMENT
21  #define CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
22  #define CPU_INSTRUCTION_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
23#endif
24
25#define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS
26
27static inline size_t _CPU_cache_get_data_cache_size(uint32_t level)
28{
29  switch (level) {
30    case 0:
31      /* Fall through */
32#ifdef PPC_CACHE_DATA_L3_SIZE
33    case 3:
34      return PPC_CACHE_DATA_L3_SIZE;
35#endif
36#ifdef PPC_CACHE_DATA_L2_SIZE
37    case 2:
38      return PPC_CACHE_DATA_L2_SIZE;
39#endif
40#ifdef PPC_CACHE_DATA_L1_SIZE
41    case 1:
42      return PPC_CACHE_DATA_L1_SIZE;
43#endif
44    default:
45      return 0;
46  }
47}
48
49static inline size_t _CPU_cache_get_instruction_cache_size(uint32_t level)
50{
51  switch (level) {
52    case 0:
53      /* Fall through */
54#ifdef PPC_CACHE_INSTRUCTION_L3_SIZE
55    case 3:
56      return PPC_CACHE_INSTRUCTION_L3_SIZE;
57#endif
58#ifdef PPC_CACHE_INSTRUCTION_L2_SIZE
59    case 2:
60      return PPC_CACHE_INSTRUCTION_L2_SIZE;
61#endif
62#ifdef PPC_CACHE_INSTRUCTION_L1_SIZE
63    case 1:
64      return PPC_CACHE_INSTRUCTION_L1_SIZE;
65#endif
66    default:
67      return 0;
68  }
69}
70
71/*
72 * CACHE MANAGER: The following functions are CPU-specific.
73 * They provide the basic implementation for the rtems_* cache
74 * management routines. If a given function has no meaning for the CPU,
75 * it does nothing by default.
76 *
77 * FIXME: Some functions simply have not been implemented.
78 */
79
80#if defined(ppc603) || defined(ppc603e) || defined(mpc8260) /* And possibly others */
81
82/* Helpful macros */
83#define PPC_Get_HID0( _value ) \
84  do { \
85      _value = 0;        /* to avoid warnings */ \
86      __asm__ volatile( \
87          "mfspr %0, 0x3f0;"     /* get HID0 */ \
88          "isync" \
89          : "=r" (_value) \
90          : "0" (_value) \
91      ); \
92  } while (0)
93
94#define PPC_Set_HID0( _value ) \
95  do { \
96      __asm__ volatile( \
97          "isync;" \
98          "mtspr 0x3f0, %0;"     /* load HID0 */ \
99          "isync" \
100          : "=r" (_value) \
101          : "0" (_value) \
102      ); \
103  } while (0)
104
105static inline void _CPU_cache_enable_data(void)
106{
107  uint32_t   value;
108  PPC_Get_HID0( value );
109  value |= HID0_DCE;        /* set DCE bit */
110  PPC_Set_HID0( value );
111}
112
113static inline void _CPU_cache_disable_data(void)
114{
115  uint32_t   value;
116  PPC_Get_HID0( value );
117  value &= ~HID0_DCE;        /* clear DCE bit */
118  PPC_Set_HID0( value );
119}
120
121static inline void _CPU_cache_invalidate_entire_data(void)
122{
123  uint32_t  value;
124  PPC_Get_HID0( value );
125  value |= HID0_DCI;        /* set data flash invalidate bit */
126  PPC_Set_HID0( value );
127  value &= ~HID0_DCI;        /* clear data flash invalidate bit */
128  PPC_Set_HID0( value );
129}
130
131static inline void _CPU_cache_freeze_data(void)
132{
133  uint32_t  value;
134  PPC_Get_HID0( value );
135  value |= HID0_DLOCK;        /* set data cache lock bit */
136  PPC_Set_HID0( value );
137}
138
139static inline void _CPU_cache_unfreeze_data(void)
140{
141  uint32_t  value;
142  PPC_Get_HID0( value );
143  value &= ~HID0_DLOCK;        /* set data cache lock bit */
144  PPC_Set_HID0( value );
145}
146
147static inline void _CPU_cache_flush_entire_data(void)
148{
149  /*
150   * FIXME: how can we do this?
151   */
152}
153
154static inline void _CPU_cache_enable_instruction(void)
155{
156  uint32_t   value;
157  PPC_Get_HID0( value );
158  value |= 0x00008000;       /* Set ICE bit */
159  PPC_Set_HID0( value );
160}
161
162static inline void _CPU_cache_disable_instruction(void)
163{
164  uint32_t   value;
165  PPC_Get_HID0( value );
166  value &= 0xFFFF7FFF;       /* Clear ICE bit */
167  PPC_Set_HID0( value );
168}
169
170static inline void _CPU_cache_invalidate_entire_instruction(void)
171{
172  uint32_t  value;
173  PPC_Get_HID0( value );
174  value |= HID0_ICFI;        /* set data flash invalidate bit */
175  PPC_Set_HID0( value );
176  value &= ~HID0_ICFI;        /* clear data flash invalidate bit */
177  PPC_Set_HID0( value );
178}
179
180static inline void _CPU_cache_freeze_instruction(void)
181{
182  uint32_t  value;
183  PPC_Get_HID0( value );
184  value |= HID0_ILOCK;        /* set instruction cache lock bit */
185  PPC_Set_HID0( value );
186}
187
188static inline void _CPU_cache_unfreeze_instruction(void)
189{
190  uint32_t  value;
191  PPC_Get_HID0( value );
192  value &= ~HID0_ILOCK;        /* set instruction cache lock bit */
193  PPC_Set_HID0( value );
194}
195
196#elif ( defined(mpx8xx) || defined(mpc860) || defined(mpc821) )
197
198#define mtspr(_spr,_reg) \
199  __asm__ volatile ( "mtspr %0, %1\n" : : "i" ((_spr)), "r" ((_reg)) )
200#define isync \
201  __asm__ volatile ("isync\n"::)
202
203static inline void _CPU_cache_flush_entire_data(void) {}
204static inline void _CPU_cache_invalidate_entire_data(void) {}
205static inline void _CPU_cache_freeze_data(void) {}
206static inline void _CPU_cache_unfreeze_data(void) {}
207
208static inline void _CPU_cache_enable_data(void)
209{
210  uint32_t   r1;
211  r1 = (0x2<<24);
212  mtspr( 568, r1 );
213  isync;
214}
215
216static inline void _CPU_cache_disable_data(void)
217{
218  uint32_t   r1;
219  r1 = (0x4<<24);
220  mtspr( 568, r1 );
221  isync;
222}
223
224static inline void _CPU_cache_invalidate_entire_instruction(void) {}
225static inline void _CPU_cache_freeze_instruction(void) {}
226static inline void _CPU_cache_unfreeze_instruction(void) {}
227
228static inline void _CPU_cache_enable_instruction(void)
229{
230  uint32_t   r1;
231  r1 = (0x2<<24);
232  mtspr( 560, r1 );
233  isync;
234}
235
236static inline void _CPU_cache_disable_instruction(void)
237{
238  uint32_t   r1;
239  r1 = (0x4<<24);
240  mtspr( 560, r1 );
241  isync;
242}
243
244#else
245
246static inline void _CPU_cache_flush_entire_data(void)
247{
248        /* Void */
249}
250
251static inline void _CPU_cache_invalidate_entire_data(void)
252{
253        /* Void */
254}
255
256static inline void _CPU_cache_freeze_data(void)
257{
258        /* Void */
259}
260
261static inline void _CPU_cache_unfreeze_data(void)
262{
263        /* Void */
264}
265
266static inline void _CPU_cache_enable_data(void)
267{
268        /* Void */
269}
270
271static inline void _CPU_cache_disable_data(void)
272{
273        /* Void */
274}
275
276static inline void _CPU_cache_invalidate_entire_instruction(void)
277{
278        /* Void */
279}
280
281static inline void _CPU_cache_freeze_instruction(void)
282{
283        /* Void */
284}
285
286static inline void _CPU_cache_unfreeze_instruction(void)
287{
288        /* Void */
289}
290
291static inline void _CPU_cache_enable_instruction(void)
292{
293        /* Void */
294}
295
296static inline void _CPU_cache_disable_instruction(void)
297{
298        /* Void */
299}
300
301#endif
302
303static inline void _CPU_cache_invalidate_1_data_line(const void *addr)
304{
305  __asm__ volatile ( "dcbi 0,%0" :: "r" (addr) : "memory" );
306}
307
308static inline void _CPU_cache_flush_1_data_line(const void *addr)
309{
310  __asm__ volatile ( "dcbf 0,%0" :: "r" (addr) : "memory" );
311}
312
313
314static inline void _CPU_cache_invalidate_1_instruction_line(const void *addr)
315{
316  __asm__ volatile ( "icbi 0,%0" :: "r" (addr) : "memory");
317}
318
319#include "../../../bsps/shared/cache/cacheimpl.h"
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