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start.S @ ff081aee

Last change on this file since ff081aee was ff081aee, checked in by Sebastian Huber <sebastian.huber@…>, on 11/06/18 at 15:58:02

score: Rename interrupt stack symbols

Rename

_Configuration_Interrupt_stack_area_begin in _ISR_Stack_area_begin,
_Configuration_Interrupt_stack_area_end in _ISR_Stack_area_end, and
_Configuration_Interrupt_stack_size in _ISR_Stack_size.

Move definitions to <rtems/score/isr.h>. The new names are considerable
shorter and in the right namespace.

Update #3459.

Property mode set to 100644

File size: 12.4 KB

Line
1	/**
2	* @file
3	*
4	* @ingroup qoriq
5	*
6	* @brief BSP start.
7	*/
8
9	/*
10	* Copyright (c) 2010, 2017 embedded brains GmbH. All rights reserved.
11	*
12	* embedded brains GmbH
13	* Dornierstr. 4
14	* 82178 Puchheim
15	* Germany
16	* <rtems@embedded-brains.de>
17	*
18	* The license and distribution terms for this file may be
19	* found in the file LICENSE in this distribution or at
20	* http://www.rtems.org/license/LICENSE.
21	*/
22
23	#include <rtems/score/percpu.h>
24
25	#include <bsp.h>
26
27	#include <libcpu/powerpc-utility.h>
28
29	#include <bsp/vectors.h>
30
31	#if (QORIQ_INITIAL_MSR & MSR_FP) != 0
32	#define INITIALIZE_FPU
33	#endif
34
35	#define FIRST_TLB 0
36	#define SCRATCH_TLB QORIQ_TLB1_ENTRY_COUNT - 1
37	#define INITIAL_MSR r14
38	#define START_STACK r15
39	#define SAVED_LINK_REGISTER r16
40	#define FDT_REGISTER r17
41	#define CPU_SELF r18
42
43	.globl _start
44	#ifdef RTEMS_SMP
45	#if QORIQ_THREAD_COUNT > 1
46	.globl _start_thread
47	#endif
48	.globl _start_secondary_processor
49	#endif
50	.globl bsp_exc_vector_base
51
52	.section ".bsp_start_text", "ax"
53
54	_start:
55	mr FDT_REGISTER, r3
56	bl .Linitearly
57
58	/* Get start stack */
59	LA START_STACK, _ISR_Stack_area_begin
60	LA r3, _ISR_Stack_size
61	add START_STACK, START_STACK, r3
62
63	bl .Linitmore
64
65	/* Copy fast text */
66	LA r3, bsp_section_fast_text_begin
67	LA r4, bsp_section_fast_text_load_begin
68	LA r5, bsp_section_fast_text_size
69	bl .Lcopy
70	LA r3, bsp_section_fast_text_begin
71	LA r4, bsp_section_fast_text_size
72	bl rtems_cache_flush_multiple_data_lines
73	PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
74
75	/* Copy read-only data */
76	LA r3, bsp_section_rodata_begin
77	LA r4, bsp_section_rodata_load_begin
78	LA r5, bsp_section_rodata_size
79	bl .Lcopy
80
81	/* Copy FDT into read-only data */
82	mr r3, FDT_REGISTER
83	bl bsp_fdt_copy
84	PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
85
86	/* Flush read-only data */
87	LA r3, bsp_section_rodata_begin
88	LA r4, bsp_section_rodata_size
89	bl rtems_cache_flush_multiple_data_lines
90	PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
91
92	/* Copy fast data */
93	LA r3, bsp_section_fast_data_begin
94	LA r4, bsp_section_fast_data_load_begin
95	LA r5, bsp_section_fast_data_size
96	bl .Lcopy
97
98	/* Copy data */
99	LA r3, bsp_section_data_begin
100	LA r4, bsp_section_data_load_begin
101	LA r5, bsp_section_data_size
102	bl .Lcopy
103
104	/* NULL pointer access protection (only core 0 has to do this) */
105	mfspr r3, BOOKE_PIR
106	cmpwi r3, 0
107	bne .Lnull_area_setup_done
108	LA r3, bsp_section_start_begin
109	srawi r3, r3, 2
110	mtctr r3
111	li r3, -4
112	LWI r4, 0x44000002
113	.Lnull_area_setup_loop:
114	stwu r4, 4(r3)
115	bdnz .Lnull_area_setup_loop
116	.Lnull_area_setup_done:
117
118	li r3, 1
119	bl .Linitmmu
120
121	/* Clear SBSS */
122	LA r3, bsp_section_sbss_begin
123	LA r4, bsp_section_sbss_size
124	bl bsp_start_zero
125	PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
126
127	/* Clear BSS */
128	LA r3, bsp_section_bss_begin
129	LA r4, bsp_section_bss_size
130	bl bsp_start_zero
131	PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
132
133	#ifndef __powerpc64__
134	/* Set up EABI and SYSV environment */
135	bl __eabi
136	#endif
137
138	/* Clear command line */
139	li r3, 0
140
141	bl boot_card
142	PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
143
144	.Lcopy:
145	PPC_REG_CMP r3, r4
146	beqlr
147	b memcpy
148	PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
149
150	.Linitearly:
151	#ifdef __powerpc64__
152	/* Enable 64-bit computation mode for exceptions */
153	mfspr r0, BOOKE_EPCR
154	oris r0, r0, BOOKE_EPCR_ICM >> 16
155	mtspr BOOKE_EPCR, r0
156
157	/* Enable 64-bit computation mode */
158	mfmsr r0
159	oris r0, r0, MSR_CM >> 16
160	mtmsr r0
161	isync
162	#endif
163
164	/* Disable decrementer */
165	mfspr r0, BOOKE_TCR
166	LWI r4, BOOKE_TCR_DIE
167	andc r0, r0, r4
168	mtspr BOOKE_TCR, r0
169
170	#ifdef QORIQ_INITIAL_SPEFSCR
171	/* SPEFSCR initialization */
172	LWI r0, QORIQ_INITIAL_SPEFSCR
173	mtspr FSL_EIS_SPEFSCR, r0
174	#endif
175
176	#ifdef QORIQ_INITIAL_BUCSR
177	/* BUCSR initialization */
178	LWI r0, QORIQ_INITIAL_BUCSR
179	mtspr FSL_EIS_BUCSR, r0
180	isync
181	#endif
182
183	#if defined(QORIQ_INITIAL_HID0) && !defined(QORIQ_IS_HYPERVISOR_GUEST)
184	/* HID0 initialization */
185	LWI r0, QORIQ_INITIAL_HID0
186	mtspr HID0, r0
187	#endif
188
189	#ifdef __powerpc64__
190	LA32 r2, .TOC.
191	#else
192	/* Invalidate TLS anchor */
193	li r2, 0
194
195	/* Set small-data anchor */
196	LA r13, _SDA_BASE_
197	#endif
198
199	SET_SELF_CPU_CONTROL CPU_SELF, r5
200
201	blr
202
203	.Linitmore:
204	mflr SAVED_LINK_REGISTER
205
206	/* Invalidate all TS1 MMU entries */
207	li r3, 1
208	bl qoriq_tlb1_invalidate_all_by_ts
209	PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
210
211	/* Add TS1 entry for the first 4GiB of RAM */
212	li r3, SCRATCH_TLB
213	li r4, FSL_EIS_MAS1_TS
214	li r5, FSL_EIS_MAS2_M
215	li r6, FSL_EIS_MAS3_SR \| FSL_EIS_MAS3_SW \| FSL_EIS_MAS3_SX
216	li r7, 0
217	li r8, 0
218	li r9, 11
219	bl qoriq_tlb1_write
220	PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
221
222	/* MSR initialization and use TS1 for address translation */
223	LWI INITIAL_MSR, QORIQ_INITIAL_MSR
224	ori r0, INITIAL_MSR, MSR_IS \| MSR_DS
225	#ifdef QORIQ_IS_HYPERVISOR_GUEST
226	oris r0, r0, MSR_GS >> 16
227	#endif
228	mtmsr r0
229	isync
230
231	/*
232	* Initialize start stack. The stacks are statically allocated and
233	* properly aligned.
234	*/
235	subi r1, START_STACK, PPC_DEFAULT_CACHE_LINE_SIZE
236	li r0, 0
237	PPC_REG_STORE r0, 0(r1)
238
239	#ifdef INITIALIZE_FPU
240	bl .Linitfpu
241	#endif
242
243	mtlr SAVED_LINK_REGISTER
244	blr
245
246	.Linitmmu:
247	mflr SAVED_LINK_REGISTER
248
249	/* Configure MMU */
250	li r4, FIRST_TLB
251	li r5, SCRATCH_TLB
252	bl qoriq_mmu_config
253	PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
254	mtmsr INITIAL_MSR
255	isync
256	li r3, SCRATCH_TLB
257	bl qoriq_tlb1_invalidate
258	PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
259
260	mtlr SAVED_LINK_REGISTER
261	blr
262
263	#ifdef INITIALIZE_FPU
264	/*
265	* Write a value to the FPRs to initialize the hidden tag bits. See
266	* also "Core Software Initialization Requirements" of the e500mc
267	* reference manual for example.
268	*/
269	.Linitfpu:
270	li r0, 0
271	stw r0, 0(r1)
272	stw r0, 4(r1)
273	lfd f0, 0(r1)
274	fmr f1, f0
275	fmr f2, f0
276	fmr f3, f0
277	fmr f4, f0
278	fmr f5, f0
279	fmr f6, f0
280	fmr f7, f0
281	fmr f8, f0
282	fmr f9, f0
283	fmr f10, f0
284	fmr f11, f0
285	fmr f12, f0
286	fmr f13, f0
287	fmr f14, f0
288	fmr f15, f0
289	fmr f16, f0
290	fmr f17, f0
291	fmr f18, f0
292	fmr f19, f0
293	fmr f20, f0
294	fmr f21, f0
295	fmr f22, f0
296	fmr f23, f0
297	fmr f24, f0
298	fmr f25, f0
299	fmr f26, f0
300	fmr f27, f0
301	fmr f28, f0
302	fmr f29, f0
303	fmr f30, f0
304	fmr f31, f0
305	blr
306	#endif
307
308	#ifdef RTEMS_SMP
309	#if QORIQ_THREAD_COUNT > 1
310	_start_thread:
311	/* Adjust PIR */
312	mfspr r0, BOOKE_PIR
313	srawi r0, r0, 2
314	ori r0, r0, 1
315	mtspr BOOKE_PIR, r0
316
317	bl .Linitearly
318
319	/* Initialize start stack */
320	PPC_REG_LOAD r3, PER_CPU_INTERRUPT_STACK_HIGH(CPU_SELF)
321	subi r1, r3, PPC_MINIMUM_STACK_FRAME_SIZE
322	clrrwi r1, r1, PPC_STACK_ALIGN_POWER
323	li r0, 0
324	PPC_REG_STORE r0, 0(r1)
325
326	#ifdef INITIALIZE_FPU
327	bl .Linitfpu
328	#endif
329
330	mr r3, CPU_SELF
331	b qoriq_start_thread
332	PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
333	#endif
334	_start_secondary_processor:
335	bl .Linitearly
336
337	/* Get start stack */
338	mr START_STACK, r3
339
340	bl .Linitmore
341	li r3, 0
342	bl .Linitmmu
343	mr r3, CPU_SELF
344	b bsp_start_on_secondary_processor
345	PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
346	#endif /* RTEMS_SMP */
347
348	#ifdef __powerpc64__
349	#define START_NOP_FOR_LINKER_TOC_POINTER_RESTORE nop; nop; nop; nop
350	#else
351	#define START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
352	#endif
353
354	/* Exception vector prologues area */
355	.section ".bsp_start_text", "ax"
356	.align 4
357	bsp_exc_vector_base:
358	/* Critical input */
359	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
360	PPC_REG_STORE r3, GPR3_OFFSET(r1)
361	li r3, 0
362	b ppc_exc_fatal_critical
363	START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
364	/* Machine check */
365	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
366	PPC_REG_STORE r3, GPR3_OFFSET(r1)
367	li r3, 1
368	b ppc_exc_fatal_machine_check
369	START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
370	/* Data storage */
371	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
372	PPC_REG_STORE r3, GPR3_OFFSET(r1)
373	li r3, 2
374	b ppc_exc_fatal_normal
375	START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
376	/* Instruction storage */
377	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
378	PPC_REG_STORE r3, GPR3_OFFSET(r1)
379	li r3, 3
380	b ppc_exc_fatal_normal
381	START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
382	/* External input */
383	PPC_REG_STORE_UPDATE r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1)
384	PPC_REG_STORE r3, PPC_EXC_GPR3_PROLOGUE_OFFSET(r1)
385	li r3, 4
386	b ppc_exc_interrupt
387	START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
388	/* Alignment */
389	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
390	PPC_REG_STORE r3, GPR3_OFFSET(r1)
391	li r3, 5
392	b ppc_exc_fatal_normal
393	START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
394	/* Program */
395	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
396	PPC_REG_STORE r3, GPR3_OFFSET(r1)
397	li r3, 6
398	b ppc_exc_fatal_normal
399	START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
400	#ifdef __PPC_CPU_E6500__
401	/* Floating-point unavailable */
402	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
403	PPC_REG_STORE r3, GPR3_OFFSET(r1)
404	li r3, 7
405	b ppc_exc_fatal_normal
406	START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
407	#endif
408	/* System call */
409	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
410	PPC_REG_STORE r3, GPR3_OFFSET(r1)
411	li r3, 8
412	b ppc_exc_fatal_normal
413	START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
414	#ifdef __PPC_CPU_E6500__
415	/* APU unavailable */
416	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
417	PPC_REG_STORE r3, GPR3_OFFSET(r1)
418	li r3, 9
419	b ppc_exc_fatal_normal
420	START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
421	#endif
422	/* Decrementer */
423	#ifdef QORIQ_IS_HYPERVISOR_GUEST
424	PPC_REG_STORE_UPDATE r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1)
425	PPC_REG_STORE r3, PPC_EXC_GPR3_PROLOGUE_OFFSET(r1)
426	li r3, 10
427	b ppc_exc_interrupt
428	#else
429	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
430	PPC_REG_STORE r3, GPR3_OFFSET(r1)
431	li r3, 10
432	b ppc_exc_fatal_normal
433	#endif
434	START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
435	/* Fixed-interval timer interrupt */
436	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
437	PPC_REG_STORE r3, GPR3_OFFSET(r1)
438	li r3, 11
439	b ppc_exc_fatal_normal
440	START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
441	/* Watchdog timer interrupt */
442	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
443	PPC_REG_STORE r3, GPR3_OFFSET(r1)
444	li r3, 12
445	b ppc_exc_fatal_critical
446	START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
447	/* Data TLB error */
448	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
449	PPC_REG_STORE r3, GPR3_OFFSET(r1)
450	li r3, 13
451	b ppc_exc_fatal_normal
452	START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
453	/* Instruction TLB error */
454	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
455	PPC_REG_STORE r3, GPR3_OFFSET(r1)
456	li r3, 14
457	b ppc_exc_fatal_normal
458	START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
459	/* Debug */
460	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
461	PPC_REG_STORE r3, GPR3_OFFSET(r1)
462	li r3, 15
463	b ppc_exc_fatal_debug
464	START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
465	/* SPE APU unavailable or AltiVec unavailable */
466	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
467	PPC_REG_STORE r3, GPR3_OFFSET(r1)
468	li r3, 32
469	b ppc_exc_fatal_normal
470	START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
471	/* SPE floating-point data exception or AltiVec assist */
472	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
473	PPC_REG_STORE r3, GPR3_OFFSET(r1)
474	li r3, 33
475	b ppc_exc_fatal_normal
476	START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
477	#ifndef __PPC_CPU_E6500__
478	/* SPE floating-point round exception */
479	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
480	PPC_REG_STORE r3, GPR3_OFFSET(r1)
481	li r3, 34
482	b ppc_exc_fatal_normal
483	START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
484	#endif
485	/* Performance monitor */
486	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
487	PPC_REG_STORE r3, GPR3_OFFSET(r1)
488	li r3, 35
489	b ppc_exc_fatal_normal
490	START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
491	#ifdef __PPC_CPU_E6500__
492	/* Processor doorbell interrupt */
493	#if defined(QORIQ_IS_HYPERVISOR_GUEST) && defined(RTEMS_SMP)
494	PPC_REG_STORE_UPDATE r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1)
495	PPC_REG_STORE r3, PPC_EXC_GPR3_PROLOGUE_OFFSET(r1)
496	li r3, 36
497	b ppc_exc_interrupt
498	#else
499	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
500	PPC_REG_STORE r3, GPR3_OFFSET(r1)
501	li r3, 36
502	b ppc_exc_fatal_normal
503	#endif
504	START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
505	/* Processor doorbell critical interrupt */
506	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
507	PPC_REG_STORE r3, GPR3_OFFSET(r1)
508	li r3, 37
509	b ppc_exc_fatal_critical
510	START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
511	/* Guest processor doorbell */
512	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
513	PPC_REG_STORE r3, GPR3_OFFSET(r1)
514	li r3, 38
515	b ppc_exc_fatal_normal
516	START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
517	/* Guest processor doorbell critical and machine check */
518	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
519	PPC_REG_STORE r3, GPR3_OFFSET(r1)
520	li r3, 39
521	b ppc_exc_fatal_critical
522	START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
523	/* Hypervisor system call */
524	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
525	PPC_REG_STORE r3, GPR3_OFFSET(r1)
526	li r3, 40
527	b ppc_exc_fatal_normal
528	START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
529	/* Hypervisor privilege */
530	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
531	PPC_REG_STORE r3, GPR3_OFFSET(r1)
532	li r3, 41
533	b ppc_exc_fatal_normal
534	START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
535	/* LRAT error */
536	PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
537	PPC_REG_STORE r3, GPR3_OFFSET(r1)
538	li r3, 42
539	b ppc_exc_fatal_normal
540	START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
541	#endif
542
543	/* Symbol provided for debugging and tracing */
544	bsp_exc_vector_end:

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