1 | /* |
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2 | * Copyright (c) 2016 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * embedded brains GmbH |
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5 | * Dornierstr. 4 |
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6 | * 82178 Puchheim |
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7 | * Germany |
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8 | * <rtems@embedded-brains.de> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #include <libcpu/powerpc-utility.h> |
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16 | |
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17 | #define FIRST_TLB 0 |
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18 | |
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19 | #define SCRATCH_TLB QORIQ_TLB1_ENTRY_COUNT - 1 |
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20 | |
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21 | .global qoriq_restart_secondary_processor |
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22 | |
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23 | .section ".bsp_start_text", "ax" |
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24 | |
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25 | qoriq_restart_secondary_processor: |
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26 | |
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27 | mr r14, r3 |
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28 | |
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29 | /* Invalidate all TS1 MMU entries */ |
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30 | li r3, 1 |
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31 | bl qoriq_tlb1_invalidate_all_by_ts |
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32 | |
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33 | /* Add TS1 entry for the first 4GiB of RAM */ |
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34 | li r3, SCRATCH_TLB |
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35 | li r4, FSL_EIS_MAS1_TS |
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36 | li r5, FSL_EIS_MAS2_I |
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37 | li r6, FSL_EIS_MAS3_SR | FSL_EIS_MAS3_SW | FSL_EIS_MAS3_SX |
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38 | li r7, 0 |
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39 | li r8, 0 |
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40 | li r9, 11 |
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41 | bl qoriq_tlb1_write |
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42 | |
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43 | bl qoriq_l1cache_invalidate |
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44 | |
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45 | /* Set MSR and use TS1 for address translation */ |
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46 | LWI r0, QORIQ_INITIAL_MSR | MSR_IS | MSR_DS |
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47 | mtmsr r0 |
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48 | isync |
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49 | |
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50 | /* Invalidate all TS0 MMU entries */ |
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51 | li r3, 0 |
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52 | bl qoriq_tlb1_invalidate_all_by_ts |
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53 | |
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54 | /* Add TS0 entry for the first 4GiB of RAM */ |
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55 | li r3, FIRST_TLB |
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56 | li r4, 0 |
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57 | li r5, FSL_EIS_MAS2_I |
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58 | li r6, FSL_EIS_MAS3_SR | FSL_EIS_MAS3_SW | FSL_EIS_MAS3_SX |
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59 | li r7, 0 |
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60 | li r8, 0 |
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61 | li r9, 11 |
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62 | bl qoriq_tlb1_write |
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63 | |
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64 | /* Use TS0 for address translation */ |
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65 | LWI r0, QORIQ_INITIAL_MSR |
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66 | mtmsr r0 |
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67 | isync |
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68 | |
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69 | bl qoriq_l1cache_invalidate |
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70 | |
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71 | /* Wait for restart request */ |
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72 | li r0, 0 |
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73 | .Lrestartagain: |
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74 | lwz r4, 4(r14) |
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75 | cmpw r0, r4 |
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76 | beq .Lrestartagain |
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77 | isync |
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78 | mtctr r4 |
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79 | lwz r3, 12(r14) |
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80 | bctr |
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