source: rtems/bsps/powerpc/qoriq/irq/irq.c @ 23ec04c

Last change on this file since 23ec04c was 23ec04c, checked in by Sebastian Huber <sebastian.huber@…>, on 07/06/21 at 16:39:57

bsps/irq: bsp_interrupt_get_affinity()

Return a status code for bsp_interrupt_get_affinity().

Update #3269.

  • Property mode set to 100644
File size: 12.2 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup RTEMSBSPsPowerPCQorIQ
5 *
6 * @brief Interrupt implementation.
7 */
8
9/*
10 * Copyright (c) 2010, 2017 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Dornierstr. 4
14 *  82178 Puchheim
15 *  Germany
16 *  <rtems@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.org/license/LICENSE.
21 */
22
23#include <sys/param.h>
24
25#include <rtems.h>
26
27#include <libcpu/powerpc-utility.h>
28
29#include <asm/epapr_hcalls.h>
30
31#include <bsp.h>
32#include <bsp/irq.h>
33#include <bsp/irq-generic.h>
34#include <bsp/vectors.h>
35#include <bsp/utility.h>
36#include <bsp/qoriq.h>
37
38#ifdef RTEMS_SMP
39#include <rtems/score/smpimpl.h>
40#endif
41
42RTEMS_INTERRUPT_LOCK_DEFINE(static, lock, "QorIQ IRQ")
43
44#define SPURIOUS 0xffff
45
46#ifdef QORIQ_IS_HYPERVISOR_GUEST
47
48void bsp_interrupt_set_affinity(
49        rtems_vector_number vector,
50        const Processor_mask *affinity
51)
52{
53        uint32_t config;
54        unsigned int priority;
55        uint32_t destination;
56        uint32_t new_destination;
57        rtems_interrupt_lock_context lock_context;
58
59        new_destination = _Processor_mask_Find_last_set(affinity) - 1;
60
61        rtems_interrupt_lock_acquire(&lock, &lock_context);
62        ev_int_get_config(vector, &config, &priority, &destination);
63        ev_int_set_config(vector, config, priority, new_destination);
64        rtems_interrupt_lock_release(&lock, &lock_context);
65}
66
67rtems_status_code bsp_interrupt_get_affinity(
68        rtems_vector_number vector,
69        Processor_mask *affinity
70)
71{
72        uint32_t config;
73        unsigned int priority;
74        uint32_t destination;
75
76        ev_int_get_config(vector, &config, &priority, &destination);
77        _Processor_mask_From_uint32_t(affinity, destination, 0);
78        return RTEMS_SUCCESSFUL;
79}
80
81rtems_status_code bsp_interrupt_get_attributes(
82  rtems_vector_number         vector,
83  rtems_interrupt_attributes *attributes
84)
85{
86  return RTEMS_SUCCESSFUL;
87}
88
89rtems_status_code bsp_interrupt_is_pending(
90  rtems_vector_number vector,
91  bool               *pending
92)
93{
94  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
95  bsp_interrupt_assert(pending != NULL);
96  *pending = false;
97  return RTEMS_UNSATISFIED;
98}
99
100rtems_status_code bsp_interrupt_raise(rtems_vector_number vector)
101{
102  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
103  return RTEMS_UNSATISFIED;
104}
105
106#if defined(RTEMS_SMP)
107rtems_status_code bsp_interrupt_raise_on(
108  rtems_vector_number vector,
109  uint32_t            cpu_index
110)
111{
112  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
113  return RTEMS_UNSATISFIED;
114}
115#endif
116
117rtems_status_code bsp_interrupt_clear(rtems_vector_number vector)
118{
119  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
120  return RTEMS_UNSATISFIED;
121}
122
123rtems_status_code bsp_interrupt_vector_is_enabled(
124  rtems_vector_number vector,
125  bool               *enabled
126)
127{
128  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
129  bsp_interrupt_assert(enabled != NULL);
130  *enabled = false;
131  return RTEMS_UNSATISFIED;
132}
133
134rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
135{
136        bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
137        ev_int_set_mask(vector, 0);
138        return RTEMS_SUCCESSFUL;
139}
140
141rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
142{
143        bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
144        ev_int_set_mask(vector, 1);
145        return RTEMS_SUCCESSFUL;
146}
147
148void bsp_interrupt_dispatch(uintptr_t exception_number)
149{
150        unsigned int vector;
151
152        if (exception_number == 10) {
153                qoriq_decrementer_dispatch();
154                return;
155        }
156
157#ifdef RTEMS_SMP
158        if (exception_number == 36) {
159                _SMP_Inter_processor_interrupt_handler(_Per_CPU_Get());
160                return;
161        }
162#endif
163
164        /*
165         * This works only if the "has-external-proxy" property is present in the
166         * "epapr,hv-pic" device tree node.
167         */
168        vector = PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_EPR);
169
170        if (vector != SPURIOUS) {
171                uint32_t msr;
172
173                msr = ppc_external_exceptions_enable();
174                bsp_interrupt_handler_dispatch(vector);
175                ppc_external_exceptions_disable(msr);
176
177                ev_int_eoi(vector);
178        } else {
179                bsp_interrupt_handler_default(vector);
180        }
181}
182
183rtems_status_code bsp_interrupt_facility_initialize(void)
184{
185        unsigned int i;
186
187        for (i = 0; i < BSP_INTERRUPT_VECTOR_COUNT; ++i) {
188                uint32_t config;
189                unsigned int priority;
190                uint32_t destination;
191                unsigned int err;
192
193                err = ev_int_get_config(i, &config, &priority, &destination);
194                if (err != EV_SUCCESS)
195                        continue;
196
197                priority = QORIQ_PIC_PRIORITY_DEFAULT;
198
199                ev_int_set_config(i, config, priority, destination);
200        }
201
202        return RTEMS_SUCCESSFUL;
203}
204
205#else /* !QORIQ_IS_HYPERVISOR_GUEST */
206
207#define VPR_MSK BSP_BBIT32(0)
208#define VPR_A BSP_BBIT32(1)
209#define VPR_P BSP_BBIT32(8)
210#define VPR_S BSP_BBIT32(9)
211#define VPR_PRIORITY(val) BSP_BFLD32(val, 12, 15)
212#define VPR_PRIORITY_GET(reg) BSP_BFLD32GET(reg, 12, 15)
213#define VPR_PRIORITY_SET(reg, val) BSP_BFLD32SET(reg, val, 12, 15)
214#define VPR_VECTOR(val) BSP_BFLD32(val, 16, 31)
215#define VPR_VECTOR_GET(reg) BSP_BFLD32GET(reg, 16, 31)
216#define VPR_VECTOR_SET(reg, val) BSP_BFLD32SET(reg, val, 16, 31)
217
218#define GCR_RST BSP_BBIT32(0)
219#define GCR_M BSP_BBIT32(2)
220
221#define SRC_CFG_IDX(i) ((i) - QORIQ_IRQ_EXT_BASE)
222
223static const uint16_t src_cfg_offsets [] = {
224        [SRC_CFG_IDX(QORIQ_IRQ_EXT_0)] = 0x10000 >> 4,
225        [SRC_CFG_IDX(QORIQ_IRQ_EXT_1)] = 0x10020 >> 4,
226        [SRC_CFG_IDX(QORIQ_IRQ_EXT_2)] = 0x10040 >> 4,
227        [SRC_CFG_IDX(QORIQ_IRQ_EXT_3)] = 0x10060 >> 4,
228        [SRC_CFG_IDX(QORIQ_IRQ_EXT_4)] = 0x10080 >> 4,
229        [SRC_CFG_IDX(QORIQ_IRQ_EXT_5)] = 0x100a0 >> 4,
230        [SRC_CFG_IDX(QORIQ_IRQ_EXT_6)] = 0x100c0 >> 4,
231        [SRC_CFG_IDX(QORIQ_IRQ_EXT_7)] = 0x100e0 >> 4,
232        [SRC_CFG_IDX(QORIQ_IRQ_EXT_8)] = 0x10100 >> 4,
233        [SRC_CFG_IDX(QORIQ_IRQ_EXT_9)] = 0x10120 >> 4,
234        [SRC_CFG_IDX(QORIQ_IRQ_EXT_10)] = 0x10140 >> 4,
235        [SRC_CFG_IDX(QORIQ_IRQ_EXT_11)] = 0x10160 >> 4,
236        [SRC_CFG_IDX(QORIQ_IRQ_IPI_0)] = 0x010a0 >> 4,
237        [SRC_CFG_IDX(QORIQ_IRQ_IPI_1)] = 0x010b0 >> 4,
238        [SRC_CFG_IDX(QORIQ_IRQ_IPI_2)] = 0x010c0 >> 4,
239        [SRC_CFG_IDX(QORIQ_IRQ_IPI_3)] = 0x010d0 >> 4,
240        [SRC_CFG_IDX(QORIQ_IRQ_MI_0)] = 0x11600 >> 4,
241        [SRC_CFG_IDX(QORIQ_IRQ_MI_1)] = 0x11620 >> 4,
242        [SRC_CFG_IDX(QORIQ_IRQ_MI_2)] = 0x11640 >> 4,
243        [SRC_CFG_IDX(QORIQ_IRQ_MI_3)] = 0x11660 >> 4,
244        [SRC_CFG_IDX(QORIQ_IRQ_MI_4)] = 0x11680 >> 4,
245        [SRC_CFG_IDX(QORIQ_IRQ_MI_5)] = 0x116a0 >> 4,
246        [SRC_CFG_IDX(QORIQ_IRQ_MI_6)] = 0x116c0 >> 4,
247        [SRC_CFG_IDX(QORIQ_IRQ_MI_7)] = 0x116e0 >> 4,
248        [SRC_CFG_IDX(QORIQ_IRQ_MSI_0)] = 0x11c00 >> 4,
249        [SRC_CFG_IDX(QORIQ_IRQ_MSI_1)] = 0x11c20 >> 4,
250        [SRC_CFG_IDX(QORIQ_IRQ_MSI_2)] = 0x11c40 >> 4,
251        [SRC_CFG_IDX(QORIQ_IRQ_MSI_3)] = 0x11c60 >> 4,
252        [SRC_CFG_IDX(QORIQ_IRQ_MSI_4)] = 0x11c80 >> 4,
253        [SRC_CFG_IDX(QORIQ_IRQ_MSI_5)] = 0x11ca0 >> 4,
254        [SRC_CFG_IDX(QORIQ_IRQ_MSI_6)] = 0x11cc0 >> 4,
255        [SRC_CFG_IDX(QORIQ_IRQ_MSI_7)] = 0x11ce0 >> 4,
256        [SRC_CFG_IDX(QORIQ_IRQ_GT_A_0)] = 0x01120 >> 4,
257        [SRC_CFG_IDX(QORIQ_IRQ_GT_A_1)] = 0x01160 >> 4,
258        [SRC_CFG_IDX(QORIQ_IRQ_GT_A_2)] = 0x011a0 >> 4,
259        [SRC_CFG_IDX(QORIQ_IRQ_GT_A_3)] = 0x011e0 >> 4,
260        [SRC_CFG_IDX(QORIQ_IRQ_GT_B_0)] = 0x02120 >> 4,
261        [SRC_CFG_IDX(QORIQ_IRQ_GT_B_1)] = 0x02160 >> 4,
262        [SRC_CFG_IDX(QORIQ_IRQ_GT_B_2)] = 0x021a0 >> 4,
263        [SRC_CFG_IDX(QORIQ_IRQ_GT_B_3)] = 0x021e0 >> 4
264};
265
266static volatile qoriq_pic_src_cfg *get_src_cfg(rtems_vector_number vector)
267{
268        uint32_t n = MIN(RTEMS_ARRAY_SIZE(qoriq.pic.ii_0), QORIQ_IRQ_EXT_BASE);
269
270        if (vector < n) {
271                return &qoriq.pic.ii_0 [vector];
272        } else if (vector < QORIQ_IRQ_EXT_BASE) {
273                return &qoriq.pic.ii_1 [vector - n];
274        } else {
275                uintptr_t offs = ((uintptr_t)
276                        src_cfg_offsets [vector - QORIQ_IRQ_EXT_BASE]) << 4;
277
278                return (volatile qoriq_pic_src_cfg *) ((uintptr_t) &qoriq.pic + offs);
279        }
280}
281
282rtems_status_code qoriq_pic_set_priority(
283        rtems_vector_number vector,
284        int new_priority,
285        int *old_priority
286)
287{
288        rtems_status_code sc = RTEMS_SUCCESSFUL;
289        uint32_t old_vpr = 0;
290
291        if (bsp_interrupt_is_valid_vector(vector)) {
292                volatile qoriq_pic_src_cfg *src_cfg = get_src_cfg(vector);
293
294                if (QORIQ_PIC_PRIORITY_IS_VALID(new_priority)) {
295                        rtems_interrupt_lock_context lock_context;
296
297                        rtems_interrupt_lock_acquire(&lock, &lock_context);
298                        old_vpr = src_cfg->vpr;
299                        src_cfg->vpr = VPR_PRIORITY_SET(old_vpr, (uint32_t) new_priority);
300                        rtems_interrupt_lock_release(&lock, &lock_context);
301                } else if (new_priority < 0) {
302                        old_vpr = src_cfg->vpr;
303                } else {
304                        sc = RTEMS_INVALID_PRIORITY;
305                }
306        } else {
307                sc = RTEMS_INVALID_ID;
308        }
309
310        if (old_priority != NULL) {
311                *old_priority = (int) VPR_PRIORITY_GET(old_vpr);
312        }
313
314        return sc;
315}
316
317void bsp_interrupt_set_affinity(
318        rtems_vector_number vector,
319        const Processor_mask *affinity
320)
321{
322        volatile qoriq_pic_src_cfg *src_cfg = get_src_cfg(vector);
323
324        src_cfg->dr = _Processor_mask_To_uint32_t(affinity, 0);
325}
326
327rtems_status_code bsp_interrupt_get_affinity(
328        rtems_vector_number vector,
329        Processor_mask *affinity
330)
331{
332        volatile qoriq_pic_src_cfg *src_cfg = get_src_cfg(vector);
333
334        _Processor_mask_From_uint32_t(affinity, src_cfg->dr, 0);
335        return RTEMS_SUCCESSFUL;
336}
337
338static void pic_vector_enable(rtems_vector_number vector, uint32_t msk)
339{
340        volatile qoriq_pic_src_cfg *src_cfg = get_src_cfg(vector);
341        rtems_interrupt_lock_context lock_context;
342
343        bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
344
345        rtems_interrupt_lock_acquire(&lock, &lock_context);
346        src_cfg->vpr = (src_cfg->vpr & ~VPR_MSK) | msk;
347        rtems_interrupt_lock_release(&lock, &lock_context);
348}
349
350rtems_status_code bsp_interrupt_get_attributes(
351  rtems_vector_number         vector,
352  rtems_interrupt_attributes *attributes
353)
354{
355  return RTEMS_SUCCESSFUL;
356}
357
358rtems_status_code bsp_interrupt_is_pending(
359  rtems_vector_number vector,
360  bool               *pending
361)
362{
363  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
364  bsp_interrupt_assert(pending != NULL);
365  *pending = false;
366  return RTEMS_UNSATISFIED;
367}
368
369rtems_status_code bsp_interrupt_raise(rtems_vector_number vector)
370{
371  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
372  return RTEMS_UNSATISFIED;
373}
374
375#if defined(RTEMS_SMP)
376rtems_status_code bsp_interrupt_raise_on(
377  rtems_vector_number vector,
378  uint32_t            cpu_index
379)
380{
381  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
382  return RTEMS_UNSATISFIED;
383}
384#endif
385
386rtems_status_code bsp_interrupt_clear(rtems_vector_number vector)
387{
388  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
389  return RTEMS_UNSATISFIED;
390}
391
392rtems_status_code bsp_interrupt_vector_is_enabled(
393  rtems_vector_number vector,
394  bool               *enabled
395)
396{
397  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
398  bsp_interrupt_assert(enabled != NULL);
399  *enabled = false;
400  return RTEMS_UNSATISFIED;
401}
402
403rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
404{
405        pic_vector_enable(vector, 0);
406        return RTEMS_SUCCESSFUL;
407}
408
409rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
410{
411        pic_vector_enable(vector, VPR_MSK);
412        return RTEMS_SUCCESSFUL;
413}
414
415void bsp_interrupt_dispatch(uintptr_t exception_number)
416{
417        rtems_vector_number vector = qoriq.pic.iack;
418
419        if (vector != SPURIOUS) {
420                uint32_t msr = ppc_external_exceptions_enable();
421
422                bsp_interrupt_handler_dispatch(vector);
423
424                ppc_external_exceptions_disable(msr);
425
426                qoriq.pic.eoi = 0;
427                qoriq.pic.whoami;
428        } else {
429                bsp_interrupt_handler_default(vector);
430        }
431}
432
433static bool pic_is_ipi(rtems_vector_number vector)
434{
435        return QORIQ_IRQ_IPI_0 <= vector && vector <= QORIQ_IRQ_IPI_3;
436}
437
438static void pic_reset(void)
439{
440        qoriq.pic.gcr = GCR_RST;
441        while ((qoriq.pic.gcr & GCR_RST) != 0) {
442                /* Wait */
443        }
444}
445
446static void pic_global_timer_init(void)
447{
448        int i = 0;
449
450        qoriq.pic.tcra = 0;
451        qoriq.pic.tcrb = 0;
452
453        for (i = 0; i < 4; ++i) {
454                qoriq.pic.gta [0].bcr = GTBCR_CI;
455                qoriq.pic.gtb [0].bcr = GTBCR_CI;
456        }
457}
458
459rtems_status_code bsp_interrupt_facility_initialize(void)
460{
461        rtems_vector_number i = 0;
462        uint32_t processor_id = ppc_processor_id();
463
464        if (processor_id == 0) {
465                /* Core 0 must do the basic initialization */
466
467                pic_reset();
468
469                for (i = 0; i < BSP_INTERRUPT_VECTOR_COUNT; ++i) {
470                        volatile qoriq_pic_src_cfg *src_cfg = get_src_cfg(i);
471
472                        src_cfg->vpr = VPR_MSK | VPR_P
473                                | VPR_PRIORITY(QORIQ_PIC_PRIORITY_DEFAULT) | VPR_VECTOR(i);
474
475                        if (!pic_is_ipi(i)) {
476                                src_cfg->dr = 0x1;
477                        }
478                }
479
480                qoriq.pic.mer03 = 0xf;
481                qoriq.pic.mer47 = 0xf;
482                qoriq.pic.svr = SPURIOUS;
483                qoriq.pic.gcr = GCR_M;
484
485                pic_global_timer_init();
486        }
487
488        qoriq.pic.ctpr = 0;
489
490        for (i = 0; i < BSP_INTERRUPT_VECTOR_COUNT; ++i) {
491                qoriq.pic.iack;
492                qoriq.pic.eoi = 0;
493                qoriq.pic.whoami;
494        }
495
496        return RTEMS_SUCCESSFUL;
497}
498
499#endif /* QORIQ_IS_HYPERVISOR_GUEST */
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