1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup QorIQ |
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5 | * |
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6 | * @brief Interrupt implementation. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2010, 2017 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Dornierstr. 4 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <rtems@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.org/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #include <sys/param.h> |
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24 | |
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25 | #include <rtems.h> |
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26 | |
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27 | #include <libcpu/powerpc-utility.h> |
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28 | |
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29 | #include <asm/epapr_hcalls.h> |
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30 | |
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31 | #include <bsp.h> |
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32 | #include <bsp/irq.h> |
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33 | #include <bsp/irq-generic.h> |
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34 | #include <bsp/vectors.h> |
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35 | #include <bsp/utility.h> |
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36 | #include <bsp/qoriq.h> |
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37 | |
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38 | #ifdef RTEMS_SMP |
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39 | #include <rtems/score/smpimpl.h> |
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40 | #endif |
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41 | |
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42 | RTEMS_INTERRUPT_LOCK_DEFINE(static, lock, "QorIQ IRQ") |
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43 | |
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44 | #define SPURIOUS 0xffff |
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45 | |
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46 | #ifdef QORIQ_IS_HYPERVISOR_GUEST |
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47 | |
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48 | void bsp_interrupt_set_affinity( |
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49 | rtems_vector_number vector, |
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50 | const Processor_mask *affinity |
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51 | ) |
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52 | { |
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53 | uint32_t config; |
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54 | unsigned int priority; |
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55 | uint32_t destination; |
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56 | uint32_t new_destination; |
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57 | rtems_interrupt_lock_context lock_context; |
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58 | |
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59 | new_destination = _Processor_mask_Find_last_set(affinity) - 1; |
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60 | |
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61 | rtems_interrupt_lock_acquire(&lock, &lock_context); |
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62 | ev_int_get_config(vector, &config, &priority, &destination); |
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63 | ev_int_set_config(vector, config, priority, new_destination); |
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64 | rtems_interrupt_lock_release(&lock, &lock_context); |
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65 | } |
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66 | |
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67 | void bsp_interrupt_get_affinity( |
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68 | rtems_vector_number vector, |
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69 | Processor_mask *affinity |
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70 | ) |
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71 | { |
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72 | uint32_t config; |
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73 | unsigned int priority; |
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74 | uint32_t destination; |
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75 | |
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76 | ev_int_get_config(vector, &config, &priority, &destination); |
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77 | _Processor_mask_From_uint32_t(affinity, destination, 0); |
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78 | } |
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79 | |
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80 | void bsp_interrupt_vector_enable(rtems_vector_number vector) |
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81 | { |
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82 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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83 | ev_int_set_mask(vector, 0); |
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84 | } |
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85 | |
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86 | void bsp_interrupt_vector_disable(rtems_vector_number vector) |
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87 | { |
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88 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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89 | ev_int_set_mask(vector, 1); |
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90 | } |
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91 | |
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92 | void bsp_interrupt_dispatch(uintptr_t exception_number) |
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93 | { |
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94 | unsigned int vector; |
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95 | |
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96 | if (exception_number == 10) { |
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97 | qoriq_decrementer_dispatch(); |
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98 | return; |
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99 | } |
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100 | |
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101 | #ifdef RTEMS_SMP |
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102 | if (exception_number == 36) { |
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103 | _SMP_Inter_processor_interrupt_handler(); |
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104 | return; |
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105 | } |
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106 | #endif |
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107 | |
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108 | /* |
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109 | * This works only if the "has-external-proxy" property is present in the |
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110 | * "epapr,hv-pic" device tree node. |
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111 | */ |
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112 | vector = PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_EPR); |
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113 | |
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114 | if (vector != SPURIOUS) { |
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115 | uint32_t msr; |
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116 | |
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117 | msr = ppc_external_exceptions_enable(); |
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118 | bsp_interrupt_handler_dispatch(vector); |
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119 | ppc_external_exceptions_disable(msr); |
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120 | |
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121 | ev_int_eoi(vector); |
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122 | } else { |
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123 | bsp_interrupt_handler_default(vector); |
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124 | } |
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125 | } |
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126 | |
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127 | rtems_status_code bsp_interrupt_facility_initialize(void) |
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128 | { |
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129 | unsigned int i; |
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130 | |
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131 | for (i = BSP_INTERRUPT_VECTOR_MIN; i <= BSP_INTERRUPT_VECTOR_MAX; ++i) { |
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132 | uint32_t config; |
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133 | unsigned int priority; |
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134 | uint32_t destination; |
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135 | unsigned int err; |
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136 | |
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137 | err = ev_int_get_config(i, &config, &priority, &destination); |
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138 | if (err != EV_SUCCESS) |
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139 | continue; |
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140 | |
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141 | priority = QORIQ_PIC_PRIORITY_DEFAULT; |
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142 | |
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143 | ev_int_set_config(i, config, priority, destination); |
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144 | } |
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145 | |
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146 | return RTEMS_SUCCESSFUL; |
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147 | } |
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148 | |
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149 | #else /* !QORIQ_IS_HYPERVISOR_GUEST */ |
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150 | |
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151 | #define VPR_MSK BSP_BBIT32(0) |
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152 | #define VPR_A BSP_BBIT32(1) |
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153 | #define VPR_P BSP_BBIT32(8) |
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154 | #define VPR_S BSP_BBIT32(9) |
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155 | #define VPR_PRIORITY(val) BSP_BFLD32(val, 12, 15) |
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156 | #define VPR_PRIORITY_GET(reg) BSP_BFLD32GET(reg, 12, 15) |
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157 | #define VPR_PRIORITY_SET(reg, val) BSP_BFLD32SET(reg, val, 12, 15) |
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158 | #define VPR_VECTOR(val) BSP_BFLD32(val, 16, 31) |
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159 | #define VPR_VECTOR_GET(reg) BSP_BFLD32GET(reg, 16, 31) |
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160 | #define VPR_VECTOR_SET(reg, val) BSP_BFLD32SET(reg, val, 16, 31) |
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161 | |
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162 | #define GCR_RST BSP_BBIT32(0) |
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163 | #define GCR_M BSP_BBIT32(2) |
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164 | |
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165 | #define SRC_CFG_IDX(i) ((i) - QORIQ_IRQ_EXT_BASE) |
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166 | |
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167 | static const uint16_t src_cfg_offsets [] = { |
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168 | [SRC_CFG_IDX(QORIQ_IRQ_EXT_0)] = 0x10000 >> 4, |
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169 | [SRC_CFG_IDX(QORIQ_IRQ_EXT_1)] = 0x10020 >> 4, |
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170 | [SRC_CFG_IDX(QORIQ_IRQ_EXT_2)] = 0x10040 >> 4, |
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171 | [SRC_CFG_IDX(QORIQ_IRQ_EXT_3)] = 0x10060 >> 4, |
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172 | [SRC_CFG_IDX(QORIQ_IRQ_EXT_4)] = 0x10080 >> 4, |
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173 | [SRC_CFG_IDX(QORIQ_IRQ_EXT_5)] = 0x100a0 >> 4, |
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174 | [SRC_CFG_IDX(QORIQ_IRQ_EXT_6)] = 0x100c0 >> 4, |
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175 | [SRC_CFG_IDX(QORIQ_IRQ_EXT_7)] = 0x100e0 >> 4, |
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176 | [SRC_CFG_IDX(QORIQ_IRQ_EXT_8)] = 0x10100 >> 4, |
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177 | [SRC_CFG_IDX(QORIQ_IRQ_EXT_9)] = 0x10120 >> 4, |
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178 | [SRC_CFG_IDX(QORIQ_IRQ_EXT_10)] = 0x10140 >> 4, |
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179 | [SRC_CFG_IDX(QORIQ_IRQ_EXT_11)] = 0x10160 >> 4, |
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180 | [SRC_CFG_IDX(QORIQ_IRQ_IPI_0)] = 0x010a0 >> 4, |
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181 | [SRC_CFG_IDX(QORIQ_IRQ_IPI_1)] = 0x010b0 >> 4, |
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182 | [SRC_CFG_IDX(QORIQ_IRQ_IPI_2)] = 0x010c0 >> 4, |
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183 | [SRC_CFG_IDX(QORIQ_IRQ_IPI_3)] = 0x010d0 >> 4, |
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184 | [SRC_CFG_IDX(QORIQ_IRQ_MI_0)] = 0x11600 >> 4, |
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185 | [SRC_CFG_IDX(QORIQ_IRQ_MI_1)] = 0x11620 >> 4, |
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186 | [SRC_CFG_IDX(QORIQ_IRQ_MI_2)] = 0x11640 >> 4, |
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187 | [SRC_CFG_IDX(QORIQ_IRQ_MI_3)] = 0x11660 >> 4, |
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188 | [SRC_CFG_IDX(QORIQ_IRQ_MI_4)] = 0x11680 >> 4, |
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189 | [SRC_CFG_IDX(QORIQ_IRQ_MI_5)] = 0x116a0 >> 4, |
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190 | [SRC_CFG_IDX(QORIQ_IRQ_MI_6)] = 0x116c0 >> 4, |
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191 | [SRC_CFG_IDX(QORIQ_IRQ_MI_7)] = 0x116e0 >> 4, |
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192 | [SRC_CFG_IDX(QORIQ_IRQ_MSI_0)] = 0x11c00 >> 4, |
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193 | [SRC_CFG_IDX(QORIQ_IRQ_MSI_1)] = 0x11c20 >> 4, |
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194 | [SRC_CFG_IDX(QORIQ_IRQ_MSI_2)] = 0x11c40 >> 4, |
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195 | [SRC_CFG_IDX(QORIQ_IRQ_MSI_3)] = 0x11c60 >> 4, |
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196 | [SRC_CFG_IDX(QORIQ_IRQ_MSI_4)] = 0x11c80 >> 4, |
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197 | [SRC_CFG_IDX(QORIQ_IRQ_MSI_5)] = 0x11ca0 >> 4, |
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198 | [SRC_CFG_IDX(QORIQ_IRQ_MSI_6)] = 0x11cc0 >> 4, |
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199 | [SRC_CFG_IDX(QORIQ_IRQ_MSI_7)] = 0x11ce0 >> 4, |
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200 | [SRC_CFG_IDX(QORIQ_IRQ_GT_A_0)] = 0x01120 >> 4, |
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201 | [SRC_CFG_IDX(QORIQ_IRQ_GT_A_1)] = 0x01160 >> 4, |
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202 | [SRC_CFG_IDX(QORIQ_IRQ_GT_A_2)] = 0x011a0 >> 4, |
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203 | [SRC_CFG_IDX(QORIQ_IRQ_GT_A_3)] = 0x011e0 >> 4, |
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204 | [SRC_CFG_IDX(QORIQ_IRQ_GT_B_0)] = 0x02120 >> 4, |
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205 | [SRC_CFG_IDX(QORIQ_IRQ_GT_B_1)] = 0x02160 >> 4, |
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206 | [SRC_CFG_IDX(QORIQ_IRQ_GT_B_2)] = 0x021a0 >> 4, |
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207 | [SRC_CFG_IDX(QORIQ_IRQ_GT_B_3)] = 0x021e0 >> 4 |
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208 | }; |
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209 | |
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210 | static volatile qoriq_pic_src_cfg *get_src_cfg(rtems_vector_number vector) |
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211 | { |
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212 | uint32_t n = MIN(RTEMS_ARRAY_SIZE(qoriq.pic.ii_0), QORIQ_IRQ_EXT_BASE); |
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213 | |
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214 | if (vector < n) { |
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215 | return &qoriq.pic.ii_0 [vector]; |
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216 | } else if (vector < QORIQ_IRQ_EXT_BASE) { |
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217 | return &qoriq.pic.ii_1 [vector - n]; |
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218 | } else { |
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219 | uintptr_t offs = ((uintptr_t) |
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220 | src_cfg_offsets [vector - QORIQ_IRQ_EXT_BASE]) << 4; |
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221 | |
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222 | return (volatile qoriq_pic_src_cfg *) ((uintptr_t) &qoriq.pic + offs); |
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223 | } |
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224 | } |
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225 | |
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226 | rtems_status_code qoriq_pic_set_priority( |
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227 | rtems_vector_number vector, |
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228 | int new_priority, |
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229 | int *old_priority |
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230 | ) |
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231 | { |
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232 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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233 | uint32_t old_vpr = 0; |
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234 | |
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235 | if (bsp_interrupt_is_valid_vector(vector)) { |
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236 | volatile qoriq_pic_src_cfg *src_cfg = get_src_cfg(vector); |
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237 | |
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238 | if (QORIQ_PIC_PRIORITY_IS_VALID(new_priority)) { |
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239 | rtems_interrupt_lock_context lock_context; |
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240 | |
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241 | rtems_interrupt_lock_acquire(&lock, &lock_context); |
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242 | old_vpr = src_cfg->vpr; |
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243 | src_cfg->vpr = VPR_PRIORITY_SET(old_vpr, (uint32_t) new_priority); |
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244 | rtems_interrupt_lock_release(&lock, &lock_context); |
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245 | } else if (new_priority < 0) { |
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246 | old_vpr = src_cfg->vpr; |
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247 | } else { |
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248 | sc = RTEMS_INVALID_PRIORITY; |
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249 | } |
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250 | } else { |
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251 | sc = RTEMS_INVALID_ID; |
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252 | } |
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253 | |
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254 | if (old_priority != NULL) { |
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255 | *old_priority = (int) VPR_PRIORITY_GET(old_vpr); |
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256 | } |
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257 | |
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258 | return sc; |
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259 | } |
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260 | |
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261 | void bsp_interrupt_set_affinity( |
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262 | rtems_vector_number vector, |
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263 | const Processor_mask *affinity |
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264 | ) |
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265 | { |
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266 | volatile qoriq_pic_src_cfg *src_cfg = get_src_cfg(vector); |
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267 | |
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268 | src_cfg->dr = _Processor_mask_To_uint32_t(affinity, 0); |
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269 | } |
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270 | |
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271 | void bsp_interrupt_get_affinity( |
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272 | rtems_vector_number vector, |
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273 | Processor_mask *affinity |
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274 | ) |
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275 | { |
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276 | volatile qoriq_pic_src_cfg *src_cfg = get_src_cfg(vector); |
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277 | |
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278 | _Processor_mask_From_uint32_t(affinity, src_cfg->dr, 0); |
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279 | } |
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280 | |
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281 | static void pic_vector_enable(rtems_vector_number vector, uint32_t msk) |
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282 | { |
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283 | volatile qoriq_pic_src_cfg *src_cfg = get_src_cfg(vector); |
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284 | rtems_interrupt_lock_context lock_context; |
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285 | |
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286 | bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)); |
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287 | |
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288 | rtems_interrupt_lock_acquire(&lock, &lock_context); |
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289 | src_cfg->vpr = (src_cfg->vpr & ~VPR_MSK) | msk; |
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290 | rtems_interrupt_lock_release(&lock, &lock_context); |
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291 | } |
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292 | |
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293 | void bsp_interrupt_vector_enable(rtems_vector_number vector) |
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294 | { |
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295 | pic_vector_enable(vector, 0); |
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296 | } |
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297 | |
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298 | void bsp_interrupt_vector_disable(rtems_vector_number vector) |
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299 | { |
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300 | pic_vector_enable(vector, VPR_MSK); |
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301 | } |
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302 | |
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303 | void bsp_interrupt_dispatch(uintptr_t exception_number) |
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304 | { |
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305 | rtems_vector_number vector = qoriq.pic.iack; |
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306 | |
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307 | if (vector != SPURIOUS) { |
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308 | uint32_t msr = ppc_external_exceptions_enable(); |
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309 | |
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310 | bsp_interrupt_handler_dispatch(vector); |
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311 | |
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312 | ppc_external_exceptions_disable(msr); |
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313 | |
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314 | qoriq.pic.eoi = 0; |
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315 | qoriq.pic.whoami; |
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316 | } else { |
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317 | bsp_interrupt_handler_default(vector); |
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318 | } |
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319 | } |
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320 | |
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321 | static bool pic_is_ipi(rtems_vector_number vector) |
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322 | { |
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323 | return QORIQ_IRQ_IPI_0 <= vector && vector <= QORIQ_IRQ_IPI_3; |
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324 | } |
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325 | |
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326 | static void pic_reset(void) |
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327 | { |
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328 | qoriq.pic.gcr = GCR_RST; |
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329 | while ((qoriq.pic.gcr & GCR_RST) != 0) { |
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330 | /* Wait */ |
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331 | } |
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332 | } |
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333 | |
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334 | static void pic_global_timer_init(void) |
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335 | { |
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336 | int i = 0; |
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337 | |
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338 | qoriq.pic.tcra = 0; |
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339 | qoriq.pic.tcrb = 0; |
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340 | |
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341 | for (i = 0; i < 4; ++i) { |
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342 | qoriq.pic.gta [0].bcr = GTBCR_CI; |
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343 | qoriq.pic.gtb [0].bcr = GTBCR_CI; |
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344 | } |
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345 | } |
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346 | |
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347 | rtems_status_code bsp_interrupt_facility_initialize(void) |
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348 | { |
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349 | rtems_vector_number i = 0; |
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350 | uint32_t processor_id = ppc_processor_id(); |
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351 | |
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352 | if (processor_id == 0) { |
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353 | /* Core 0 must do the basic initialization */ |
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354 | |
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355 | pic_reset(); |
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356 | |
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357 | for (i = BSP_INTERRUPT_VECTOR_MIN; i <= BSP_INTERRUPT_VECTOR_MAX; ++i) { |
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358 | volatile qoriq_pic_src_cfg *src_cfg = get_src_cfg(i); |
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359 | |
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360 | src_cfg->vpr = VPR_MSK | VPR_P |
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361 | | VPR_PRIORITY(QORIQ_PIC_PRIORITY_DEFAULT) | VPR_VECTOR(i); |
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362 | |
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363 | if (!pic_is_ipi(i)) { |
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364 | src_cfg->dr = 0x1; |
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365 | } |
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366 | } |
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367 | |
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368 | qoriq.pic.mer03 = 0xf; |
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369 | qoriq.pic.mer47 = 0xf; |
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370 | qoriq.pic.svr = SPURIOUS; |
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371 | qoriq.pic.gcr = GCR_M; |
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372 | |
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373 | pic_global_timer_init(); |
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374 | } |
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375 | |
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376 | qoriq.pic.ctpr = 0; |
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377 | |
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378 | for (i = BSP_INTERRUPT_VECTOR_MIN; i <= BSP_INTERRUPT_VECTOR_MAX; ++i) { |
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379 | qoriq.pic.iack; |
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380 | qoriq.pic.eoi = 0; |
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381 | qoriq.pic.whoami; |
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382 | } |
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383 | |
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384 | return RTEMS_SUCCESSFUL; |
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385 | } |
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386 | |
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387 | #endif /* QORIQ_IS_HYPERVISOR_GUEST */ |
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