source: rtems/bsps/powerpc/psim/start/bspstart.c @ a2dad96

5
Last change on this file since a2dad96 was 9964895, checked in by Sebastian Huber <sebastian.huber@…>, on Apr 20, 2018 at 8:35:35 AM

bsps: Move startup files to bsps

Adjust build support files to new directory layout.

This patch is a part of the BSP source reorganization.

Update #3285.

  • Property mode set to 100644
File size: 2.7 KB
Line 
1/*
2 *  This set of routines starts the application.  It includes application,
3 *  board, and monitor specific initialization and configuration.
4 *  The generic CPU dependent initialization has been performed
5 *  before any of these are invoked.
6 *
7 *  COPYRIGHT (c) 1989-2008.
8 *  On-Line Applications Research Corporation (OAR).
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.rtems.org/license/LICENSE.
13 */
14
15#include <string.h>
16#include <fcntl.h>
17#include <bsp.h>
18#include <bsp/irq.h>
19#include <psim.h>
20#include <bsp/bootcard.h>
21#include <bsp/linker-symbols.h>
22#include <rtems/bspIo.h>
23#include <rtems/counter.h>
24#include <rtems/powerpc/powerpc.h>
25
26#include <libcpu/cpuIdent.h>
27#include <libcpu/bat.h>
28#include <libcpu/spr.h>
29
30SPR_RW(SPRG1)
31
32/*  On psim, each click of the decrementer register corresponds
33 *  to 1 instruction.  By setting this to 100, we are indicating
34 *  that we are assuming it can execute 100 instructions per
35 *  microsecond.  This corresponds to sustaining 1 instruction
36 *  per cycle at 100 Mhz.  Whether this is a good guess or not
37 *  is anyone's guess.
38 */
39extern int PSIM_INSTRUCTIONS_PER_MICROSECOND[];
40
41/*
42 * PCI Bus Frequency
43 */
44unsigned int BSP_bus_frequency;
45
46/*
47 *  Driver configuration parameters
48 */
49uint32_t   bsp_clicks_per_usec;
50
51/*
52 * Memory on this board.
53 */
54uint32_t BSP_mem_size = (uint32_t)RamSize;
55
56/*
57 * Time base divisior (how many tick for 1 second).
58 */
59unsigned int BSP_time_base_divisor;
60
61extern unsigned long __rtems_end[];
62
63/*
64 *  bsp_start
65 *
66 *  This routine does the bulk of the system initialization.
67 */
68void bsp_start( void )
69{
70  /*
71   * Note we can not get CPU identification dynamically.
72   * PVR has to be set to PPC_PSIM (0xfffe) from the device
73   * file.
74   */
75
76  get_ppc_cpu_type();
77
78  /*
79   *  initialize the device driver parameters
80   */
81  BSP_bus_frequency        = (unsigned int)PSIM_INSTRUCTIONS_PER_MICROSECOND;
82  bsp_clicks_per_usec      = BSP_bus_frequency;
83  BSP_time_base_divisor    = 1;
84  rtems_counter_initialize_converter(bsp_clicks_per_usec * 1000000);
85
86  /*
87   * Initialize default raw exception handlers.
88   */
89  ppc_exc_initialize_with_vector_base(
90    (uintptr_t) bsp_section_work_begin,
91    rtems_configuration_get_interrupt_stack_size(),
92    (void *) 0xfff00000
93  );
94
95  /*
96   * Initalize RTEMS IRQ system
97   */
98  BSP_rtems_irq_mng_init(0);
99
100  /*
101   * Setup BATs and enable MMU
102   */
103  /* Memory */
104  setdbat(0, 0x0<<24, 0x0<<24, 2<<24, _PAGE_RW);
105  setibat(0, 0x0<<24, 0x0<<24, 2<<24,        0);
106  /* PCI    */
107  setdbat(1, 0x8<<24, 0x8<<24, 1<<24,  IO_PAGE);
108  setdbat(2, 0xc<<24, 0xc<<24, 1<<24,  IO_PAGE);
109
110  _write_MSR(_read_MSR() | MSR_DR | MSR_IR);
111  __asm__ volatile("sync; isync");
112
113}
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