1 | /* |
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2 | * This set of routines starts the application. It includes application, |
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3 | * board, and monitor specific initialization and configuration. |
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4 | * The generic CPU dependent initialization has been performed |
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5 | * before any of these are invoked. |
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6 | * |
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7 | * COPYRIGHT (c) 1989-2008. |
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8 | * On-Line Applications Research Corporation (OAR). |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #include <string.h> |
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16 | #include <fcntl.h> |
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17 | #include <bsp.h> |
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18 | #include <bsp/irq.h> |
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19 | #include <psim.h> |
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20 | #include <bsp/bootcard.h> |
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21 | #include <bsp/linker-symbols.h> |
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22 | #include <rtems/bspIo.h> |
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23 | #include <rtems/counter.h> |
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24 | #include <rtems/powerpc/powerpc.h> |
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25 | |
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26 | #include <libcpu/cpuIdent.h> |
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27 | #include <libcpu/bat.h> |
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28 | #include <libcpu/spr.h> |
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29 | |
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30 | SPR_RW(SPRG1) |
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31 | |
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32 | /* On psim, each click of the decrementer register corresponds |
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33 | * to 1 instruction. By setting this to 100, we are indicating |
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34 | * that we are assuming it can execute 100 instructions per |
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35 | * microsecond. This corresponds to sustaining 1 instruction |
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36 | * per cycle at 100 Mhz. Whether this is a good guess or not |
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37 | * is anyone's guess. |
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38 | */ |
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39 | extern int PSIM_INSTRUCTIONS_PER_MICROSECOND[]; |
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40 | |
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41 | /* |
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42 | * PCI Bus Frequency |
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43 | */ |
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44 | unsigned int BSP_bus_frequency; |
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45 | |
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46 | /* |
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47 | * Driver configuration parameters |
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48 | */ |
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49 | uint32_t bsp_clicks_per_usec; |
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50 | |
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51 | /* |
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52 | * Memory on this board. |
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53 | */ |
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54 | uint32_t BSP_mem_size = (uint32_t)RamSize; |
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55 | |
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56 | /* |
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57 | * Time base divisior (how many tick for 1 second). |
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58 | */ |
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59 | unsigned int BSP_time_base_divisor; |
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60 | |
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61 | extern unsigned long __rtems_end[]; |
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62 | |
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63 | uint32_t _CPU_Counter_frequency(void) |
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64 | { |
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65 | return bsp_clicks_per_usec * 1000000; |
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66 | } |
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67 | |
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68 | /* |
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69 | * bsp_start |
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70 | * |
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71 | * This routine does the bulk of the system initialization. |
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72 | */ |
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73 | void bsp_start( void ) |
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74 | { |
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75 | /* |
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76 | * Note we can not get CPU identification dynamically. |
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77 | * PVR has to be set to PPC_PSIM (0xfffe) from the device |
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78 | * file. |
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79 | */ |
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80 | |
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81 | get_ppc_cpu_type(); |
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82 | |
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83 | /* |
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84 | * initialize the device driver parameters |
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85 | */ |
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86 | BSP_bus_frequency = (unsigned int)PSIM_INSTRUCTIONS_PER_MICROSECOND; |
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87 | bsp_clicks_per_usec = BSP_bus_frequency; |
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88 | BSP_time_base_divisor = 1; |
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89 | |
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90 | ppc_exc_initialize_with_vector_base( |
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91 | (uintptr_t) _ISR_Stack_area_begin, |
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92 | (void *) 0xfff00000 |
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93 | ); |
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94 | |
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95 | /* |
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96 | * Initalize RTEMS IRQ system |
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97 | */ |
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98 | BSP_rtems_irq_mng_init(0); |
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99 | |
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100 | /* |
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101 | * Setup BATs and enable MMU |
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102 | */ |
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103 | /* Memory */ |
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104 | setdbat(0, 0x0<<28, 0x0<<28, 1<<28, _PAGE_RW); |
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105 | setibat(0, 0x0<<28, 0x0<<28, 1<<28, 0); |
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106 | /* PCI */ |
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107 | setdbat(1, 0x08<<24, 0x08<<24, 1<<24, IO_PAGE); |
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108 | setdbat(2, 0xfc<<24, 0xfc<<24, 1<<24, IO_PAGE); |
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109 | |
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110 | _write_MSR(_read_MSR() | MSR_DR | MSR_IR); |
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111 | __asm__ volatile("sync; isync"); |
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112 | |
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113 | } |
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