source: rtems/bsps/powerpc/psim/include/tm27.h @ 5da1593

5
Last change on this file since 5da1593 was 5da1593, checked in by Joel Sherrill <joel@…>, on Aug 29, 2018 at 5:39:17 PM

psim/include/tm27.h: Fix not a prototype warnings

  • Property mode set to 100644
File size: 1.7 KB
Line 
1/*
2 * @file
3 * @ingroup powerpc_psim
4 * @brief Implementations for interrupt mechanisms for Time Test 27
5 */
6
7/*
8 *  The license and distribution terms for this file may be
9 *  found in the file LICENSE in this distribution or at
10 *  http://www.rtems.org/license/LICENSE.
11 */
12
13#ifndef _RTEMS_TMTEST27
14#error "This is an RTEMS internal file you must not include directly."
15#endif
16
17#ifndef __tm27_h
18#define __tm27_h
19
20#include <bsp/irq.h>
21
22/*
23 *  Stuff for Time Test 27
24 */
25
26#define MUST_WAIT_FOR_INTERRUPT 1
27
28static void nullFunc(void) {}
29static rtems_irq_connect_data clockIrqData = {BSP_DECREMENTER,
30                                              0,
31                                              (rtems_irq_enable)nullFunc,
32                                              (rtems_irq_disable)nullFunc,
33                                              (rtems_irq_is_enabled) nullFunc};
34
35RTEMS_INLINE_ROUTINE void Install_tm27_vector(void (*_handler)())
36{
37  clockIrqData.hdl = _handler;
38  if (!BSP_install_rtems_irq_handler (&clockIrqData)) {
39    printk("Error installing clock interrupt handler!\n");
40    rtems_fatal_error_occurred(1);
41  }
42}
43
44#define Cause_tm27_intr()  \
45  do { \
46    uint32_t _clicks = 1; \
47    __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
48  } while (0)
49
50
51#define Clear_tm27_intr() \
52  do { \
53    uint32_t _clicks = 0xffffffff; \
54    __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
55  } while (0)
56
57#define Lower_tm27_intr() \
58  do { \
59    uint32_t _msr = 0; \
60    _ISR_Set_level( 0 ); \
61    __asm__ volatile( "mfmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \
62    _msr |=  0x8002; \
63    __asm__ volatile( "mtmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \
64  } while (0)
65
66#endif
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